On Fri, Aug 12, 2016 at 02:20:34PM +0530, deepak.s@xxxxxxxxxxxxxxx wrote:
> From: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
>
> With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
> So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
>
> This reverts commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44.
>
> commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44
> Author: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
> Date: Sat May 9 18:15:46 2015 +0530
>
> drm/i915/chv: Set min freq to efficient frequency on chv
>
> Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 81ab119..e59799a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5579,6 +5579,24 @@ static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
> return rp1;
> }
>
> +static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
Return int, but compute a u32? Just inconsistent.
> +{
> + struct drm_device *dev = &dev_priv->drm;
struct pci_device *pdev = dev_priv->drm.pdev;
> + u32 val, rpn;
> +
> + if (dev->pdev->revision >= 0x20) {
> + val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
> + rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
> + FB_GFX_FREQ_FUSE_MASK);
> + } else { /* For pre-production hardware */
} else { /* For pre-production hardware use RPe instead */
> + val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
> + rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
> + PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
> + }
Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
