On Wed, Aug 10, 2016 at 01:58:24PM +0100, Chris Wilson wrote:
> During intel_gt_powersave_init() we take the RPS mutex to ensure that
> all locking requirements are met as we talk to the punit, but we also
> require the struct_mutex for allocating a slice of the global GTT for a
> power context on Valleyview. struct_mutex must be the outer lock here,
> as we nest rps.mutex inside later on.
>
> Reported-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Fixes: 773ea9a80132 ("drm/i915: Perform static RPS frequency setup before...")
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1035eb5e52dd..20794804f3bb 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5675,8 +5675,6 @@ static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
> u32 pcbr;
> int pctx_size = 24*1024;
>
> - mutex_lock(&dev_priv->drm.struct_mutex);
> -
> pcbr = I915_READ(VLV_PCBR);
> if (pcbr) {
> /* BIOS set it up already, grab the pre-alloc'd space */
> @@ -5712,7 +5710,6 @@ static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
> out:
> DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
> dev_priv->vlv_pctx = pctx;
> - mutex_unlock(&dev_priv->drm.struct_mutex);
> }
>
> static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
> @@ -6488,6 +6485,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
> intel_runtime_pm_get(dev_priv);
> }
>
> + mutex_lock(&dev_priv->drm.struct_mutex);
> mutex_lock(&dev_priv->rps.hw_lock);
>
> /* Initialize RPS limits (for userspace) */
> @@ -6529,6 +6527,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
> dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
>
> mutex_unlock(&dev_priv->rps.hw_lock);
> + mutex_unlock(&dev_priv->drm.struct_mutex);
>
> intel_autoenable_gt_powersave(dev_priv);
> }
> --
> 2.8.1
--
Ville Syrjälä
Intel OTC
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