This patch series enables upfront link training on DDI platforms (SKL/BDW/HSW/BXT). They are based on some of the pacthes submitted earlier by Ander and Durgadoss. The upfront link training had to be factored out of long pulse hanlder because of deadlock issues seen on DP MST cases. Now the upfront link training takes place in intel_dp_mode_valid() to find the maximum lane count and link rate at which the DP link can be successfully trained. These values are used to prune the invalid modes before modeset. Modeset makes use the upfront lane count and link train values. These patches have been validated for DP SST on DDI platforms (SKL/HSW/BDW/BXT). They have also been tested for any regressions on non DDI platforms (CHV). Ander Conselvan de Oliveira (3): drm/i915: Don't pass crtc_state to intel_dp_set_link_params() drm/i915: Remove ddi_pll_sel from intel_crtc_state drm/i915: Split intel_ddi_pre_enable() into DP and HDMI versions Durgadoss R (2): drm/i915: Split bxt_ddi_pll_select() drm/i915/dp: Enable Upfront link training for typeC DP support on BXT Jim Bride (2): drm/i915: Split skl_get_dpll() drm/i915/dp: Enable upfront link training on SKL Manasi Navare (2): drm/i915: Split hsw_get_dpll() drm/i915: Enable upfront link training support for HSW/BDW drivers/gpu/drm/i915/intel_ddi.c | 207 +++++++++--- drivers/gpu/drm/i915/intel_display.c | 43 +-- drivers/gpu/drm/i915/intel_dp.c | 386 ++++++++++++++++------ drivers/gpu/drm/i915/intel_dp_link_training.c | 7 +- drivers/gpu/drm/i915/intel_dp_mst.c | 9 +- drivers/gpu/drm/i915/intel_dpll_mgr.c | 457 ++++++++++++++++---------- drivers/gpu/drm/i915/intel_dpll_mgr.h | 15 + drivers/gpu/drm/i915/intel_drv.h | 29 +- 8 files changed, 776 insertions(+), 377 deletions(-) -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
