Reading the Sandy Bridge documentation, on the PCH it lists 3 FDI receiver control registers (A,B,C): https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part3b_register_offsets.pdf But on the CPU side, FDI_TX_* seems undocumented but according to the linux driver, sandy bridge only has PIPE A and B. https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part2.pdf So FDI C cannot be enabled on sandy bridge? Or is there some magic to switch one of the FDI transmitters to FDI C? There was some mentioning that FDI B and C share lanes... So can you drive FDI B and C with on CPU PIPE B? Anyone can clarify this confusion? -- cinap _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
