and power up the DSI regulator when initializing a MIPI display.
v2: rebase on current drm-intel-nightly
Signed-off-by: Bob Paauwe <bob.j.paauwe@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
drivers/gpu/drm/i915/intel_dsi.c | 15 +++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f38a5e2..2caa22c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1275,11 +1275,19 @@ enum skl_disp_power_wells {
#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
#define DPIO_UPAR_SHIFT 30
+/* BXT DSI Regulator registers */
+#define BXT_DSI_CFG _MMIO(0x160020)
+#define STRAP_SELECT (1 << 0)
+
+#define BXT_DSI_TXCNTRL _MMIO(0x160054)
+#define HS_IO_CONTROL_SELECT 0x0
+
/* BXT PHY registers */
#define _BXT_PHY(phy, a, b) _MMIO_PIPE((phy), (a), (b))
#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
#define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
+#define MIPIO_RST_CTRL (1 << 2)
#define _BXT_PHY_CTL_DDI_A 0x64C00
#define _BXT_PHY_CTL_DDI_B 0x64C10
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index de8e9fb..4100ea2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -569,6 +569,21 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
I915_WRITE(DSPCLK_GATE_D, val);
}
+ if (IS_BROXTON(dev)) {
+ u32 val;
+ /*
+ * Bring the MIPI IO out of reset and power up
+ * the DSI regulator.
+ */
+ val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
+ val |= MIPIO_RST_CTRL;
+ I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
+
+ I915_WRITE(BXT_DSI_CFG, STRAP_SELECT);
+ I915_WRITE(BXT_DSI_TXCNTRL, HS_IO_CONTROL_SELECT);
+ }
+
+
/* put device in ready state */
intel_dsi_device_ready(encoder);
--
2.7.4
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