On Thu, Aug 04, 2016 at 05:46:01AM +0000, Yang, Libin wrote:
> Hi Ville,
>
> > -----Original Message-----
> > From: Ville Syrjälä [mailto:ville.syrjala@xxxxxxxxxxxxxxx]
> > Sent: Wednesday, August 3, 2016 12:59 AM
> > To: Yang, Libin <libin.yang@xxxxxxxxx>
> > Cc: libin.yang@xxxxxxxxxxxxxxx; intel-gfx@xxxxxxxxxxxxxxxxxxxxx;
> > jani.nikula@xxxxxxxxxxxxxxx; Vetter, Daniel <daniel.vetter@xxxxxxxxx>;
> > tiwai@xxxxxxx
> > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> >
> > On Tue, Aug 02, 2016 at 01:58:51PM +0000, Yang, Libin wrote:
> > > Hi Ville
> > >
> > > > -----Original Message-----
> > > > From: Ville Syrjälä [mailto:ville.syrjala@xxxxxxxxxxxxxxx]
> > > > Sent: Tuesday, August 2, 2016 6:47 PM
> > > > To: libin.yang@xxxxxxxxxxxxxxx
> > > > Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; jani.nikula@xxxxxxxxxxxxxxx;
> > > > Vetter, Daniel <daniel.vetter@xxxxxxxxx>; tiwai@xxxxxxx; Yang, Libin
> > > > <libin.yang@xxxxxxxxx>
> > > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > > >
> > > > On Tue, Aug 02, 2016 at 09:35:10AM +0800, libin.yang@xxxxxxxxxxxxxxx
> > wrote:
> > > > > From: Libin Yang <libin.yang@xxxxxxxxxxxxxxx>
> > > > >
> > > > > When modeset occurs and the LS_CLK is set to some special values
> > > > > in DP mode, the N/M need to be set manually if audio is playing.
> > > > >
> > > > > The relationship of Maud and Naud is expressed in the following
> > > > > equation:
> > > > > Maud/Naud = 512 * fs / f_LS_Clk
> > > > >
> > > > > Please refer VESA DisplayPort Standard spec for details.
> > > > >
> > > > > Also, the patch applies
> > > > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to
> > > > > APL platform.
> > > > >
> > > > > Signed-off-by: Libin Yang <libin.yang@xxxxxxxxxxxxxxx>
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_reg.h | 6 ++
> > > > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > > > +++++++++++++++++++++++++++++++------
> > > > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -7351,6 +7351,12 @@ enum {
> > > > > #define _HSW_AUD_CONFIG_B 0x65100
> > > > > #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe,
> > > > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > > > >
> > > > > +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> > > > > +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> > > > > +#define HSW_AUD_M_CTS_ENABLE(pipe)
> > _MMIO_PIPE(pipe,
> > > > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > > > +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
> > > > > +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
> > > > > +
> > > > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > > > #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> > > > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > > > b/drivers/gpu/drm/i915/intel_audio.c
> > > > > index 6700a7b..de55ecf 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > > > @@ -98,6 +98,22 @@ static const struct {
> > > > > { 192000, TMDS_297M, 20480, 247500 }, };
> > > > >
> > > > > +#define LC_540M 540000
> > > > > +#define LC_162M 162000
> > > >
> > > > Do we have some explanation why 2.7 doesn't need M/N programming,
> > > > but
> > > > 1.62 and 5.4 do?
> > >
> > > I didn't use 2.7 because I can't find a mode using 2.7.
> >
> > Hmm. Maybe we should add some knobs to force a specific bpc/link
> > rate/number of lanes to help with this kind of testing. Currently you just get
> > what you get, which isn't so nice when you want to test all variations.
> > ...
> > OK, so I just went ahead and did that. Here's a branch:
> >
> > git://github.com/vsyrjala/linux.git modparam_clock_bpp_limit
> >
> > For your DP testing just setting
> > i915.max_port_clock=162000 or i915.max_port_clock=270000 and then
> > forcing a modeset should do the trick.
>
> Thanks for the new branch. It seems download is very slow, less than
> 10Kib/s.
github that slow for you? Weird.
And I can't see a way to grab the raw patches from the github web
interface :( so I've attached the patches to this mail in case you
can't finish the git fetch in reasonable time.
> So I will submit the new patches firstly and then do the test.
> Fortunately, I found there is recommended data for 340MHz in the spec.
340 MHz? There's no such link rate for DP. I'm not sure what you're
saying here...
> I copied the data to the patch and suppose the data should be accurate.
>
> >
> > > So I can't do the test.
> > > 5.4 is for 4K and 1.62 is for 1080p.
> > >
> > > >
> > > > And I see you're only doing this on HSW+. Earlier platforms don't need this?
> > >
> > > We are not supporting earlier platforms and I'm not sure whether the
> > > old platforms supports 4K DP or not.
> >
> > SNB-IVB dotclock can go up to 360Mhz, ILK up to 405 Mhz. At least in theory.
> > The DP link is limited to 4 x 2.7 for all. From the those the dotclock limit is the
> > one you should hit first since DP can always fall back to 6bpc and that should
> > be correspond to a dotclock of 480 MHz.
> > Anyways, 360MHz is plenty for 4k@30.
> >
> >
> > The question really is why we need to do this in the first place.
> > There's nothing in the spec telling is it's really required. All I can find in the DP
> > spec is "Maud value is set to 2^15 (=32,768) when the audio clock is
> > asynchronous to the LS_Clk.", and then
>
> We made the patch because we found the HW can't calculate the value this
> will cause there is several seconds silence at the beginning of audio playback.
> With this patch, the silence is much shorter than before and is acceptable.
I see. Must be sink specific since at least my current monitor (ASUS
PB278) has no apparent delays with the current code. I guess some sinks are
just slower in clock recovery than others, and starting out with better
M/N values can speed it up a bit.
Anyways, please specify this reason for the change in the commit message,
otherwise no one can figure out why it's needed.
--
Ville Syrjälä
Intel OTC
>From 4416baa8ef415e9aa760309fc864aad8fb2ab807 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@xxxxxxxxxxxxxxx>
Date: Wed, 27 Jul 2016 17:21:21 +0300
Subject: [PATCH 1/3] drm/i915: Remove useless rate_to_index() usage
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
No need to iterate the rates array in intel_dp_max_link_rate(). We know
the max rate will be the last entry, and we already know the size.
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
Cc: Jim Bride <jim.bride@xxxxxxxxxxxxxxx>
Cc: Manasi D Navare <manasi.d.navare@xxxxxxxxx>
Cc: Durgadoss R <durgadoss.r@xxxxxxxxx>
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 001f74fc0ce5..ae3dc15fe95a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1447,7 +1447,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
if (WARN_ON(len <= 0))
return 162000;
- return rates[rate_to_index(0, rates) - 1];
+ return rates[len - 1];
}
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
--
2.7.4
>From 6b99092b0dce3edd3567da4b29ad0d5d36240f38 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@xxxxxxxxxxxxxxx>
Date: Wed, 27 Jul 2016 17:19:16 +0300
Subject: [PATCH 2/3] drm/i915: Allow rate_to_index() to return non-exact
matches
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Let's make rate_to_index() return the highest rate available that's
less than or equal to the rate requested by the caller. The function
can then be used to filter out rates higher than a certain maximum
rate.
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
Cc: Jim Bride <jim.bride@xxxxxxxxxxxxxxx>
Cc: Manasi D Navare <manasi.d.navare@xxxxxxxxx>
Cc: Durgadoss R <durgadoss.r@xxxxxxxxx>
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dp.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ae3dc15fe95a..331e0c9d1783 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1431,10 +1431,13 @@ static int rate_to_index(int find, const int *rates)
int i = 0;
for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
- if (find == rates[i])
+ if (find < rates[i])
break;
- return i;
+ if (WARN_ON(i == 0))
+ return 0;
+
+ return i - 1;
}
int
--
2.7.4
>From 4bc405c7b5fb1dcabd668bfcd50e67baae456353 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@xxxxxxxxxxxxxxx>
Date: Tue, 2 Aug 2016 18:16:32 +0300
Subject: [PATCH 3/3] drm/i915: Add
max_pipe_bpp,max_dot_clock,max_port_clock,max_lanes modparams
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Eg.
limit DP to 2.7G link rate by setting max_port_clock=270000
limit DP to use at most 2 lanes by setting set max_lanes=2
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_params.c | 13 ++++++++++++
drivers/gpu/drm/i915/i915_params.h | 4 ++++
drivers/gpu/drm/i915/intel_crt.c | 3 +++
drivers/gpu/drm/i915/intel_display.c | 13 ++++++++++++
drivers/gpu/drm/i915/intel_dp.c | 41 ++++++++++++++++++++++--------------
drivers/gpu/drm/i915/intel_dp_mst.c | 3 +++
drivers/gpu/drm/i915/intel_dsi.c | 3 +++
drivers/gpu/drm/i915/intel_dvo.c | 3 +++
drivers/gpu/drm/i915/intel_hdmi.c | 6 ++++++
drivers/gpu/drm/i915/intel_lvds.c | 3 +++
drivers/gpu/drm/i915/intel_sdvo.c | 3 +++
drivers/gpu/drm/i915/intel_tv.c | 3 +++
12 files changed, 82 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index b6e404c91eed..f9dbd308dfb6 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -63,6 +63,19 @@ struct i915_params i915 __read_mostly = {
.enable_gvt = false,
};
+module_param_named_unsafe(max_lanes, i915.max_lanes, int, 0600);
+MODULE_PARM_DESC(max_lanes,
+ "Maximum DP lanes (0=default, 1,2,4)");
+module_param_named_unsafe(max_port_clock, i915.max_port_clock, int, 0600);
+MODULE_PARM_DESC(max_port_clock,
+ "Maximum port clock limit (0=default, eg. 270000)");
+module_param_named_unsafe(max_dot_clock, i915.max_dot_clock, int, 0600);
+MODULE_PARM_DESC(max_dot_clock,
+ "Maximum dot clock limit (0=default, eg. 148500)");
+module_param_named_unsafe(max_pipe_bpp, i915.max_pipe_bpp, int, 0600);
+MODULE_PARM_DESC(max_pipe_bpp,
+ "Maximum pipe bpp used (0=default, 18,24,30,36)");
+
module_param_named(modeset, i915.modeset, int, 0400);
MODULE_PARM_DESC(modeset,
"Use kernel modesetting [KMS] (0=disable, "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 0ad020b4a925..014e821578e2 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -52,6 +52,10 @@ struct i915_params {
int mmio_debug;
int edp_vswing;
unsigned int inject_load_failure;
+ int max_lanes;
+ int max_port_clock;
+ int max_dot_clock;
+ int max_pipe_bpp;
/* leave bools at the end to not create holes */
bool enable_hangcheck;
bool fastboot;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 827b6ef4e9ae..d665a022f9dd 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -220,6 +220,9 @@ intel_crt_mode_valid(struct drm_connector *connector,
int max_dotclk = to_i915(dev)->max_dotclk_freq;
int max_clock;
+ if (i915.max_dot_clock)
+ max_dotclk = min(i915.max_dot_clock, max_dotclk);
+
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a8e8cc8dfae9..f284f1050aef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6618,6 +6618,9 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
}
}
+ if (i915.max_dot_clock)
+ clock_limit = min(i915.max_dot_clock, clock_limit);
+
if (adjusted_mode->crtc_clock > clock_limit) {
DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
adjusted_mode->crtc_clock, clock_limit,
@@ -12139,6 +12142,16 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
else
bpp = 8*3;
+ switch (i915.max_pipe_bpp) {
+ case 12*3:
+ case 10*3:
+ case 8*3:
+ case 6*3:
+ bpp = min(i915.max_pipe_bpp, bpp);
+ break;
+ default:
+ break;
+ }
pipe_config->pipe_bpp = bpp;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 331e0c9d1783..5a4bc09437f5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -150,14 +150,17 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
return max_link_bw;
}
-static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
+static int intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- u8 source_max, sink_max;
+ int source_max, sink_max;
source_max = intel_dig_port->max_lanes;
sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
+ if (i915.max_lanes > 0)
+ source_max = min(i915.max_lanes, source_max);
+
return min(source_max, sink_max);
}
@@ -201,6 +204,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ if (i915.max_dot_clock)
+ max_dotclk = min(i915.max_dot_clock, max_dotclk);
+
if (is_edp(intel_dp) && fixed_mode) {
if (mode->hdisplay > fixed_mode->hdisplay)
return MODE_PANEL;
@@ -1373,6 +1379,20 @@ static int intersect_rates(const int *source_rates, int source_len,
return k;
}
+static int rate_to_index(int find, const int *rates)
+{
+ int i = 0;
+
+ for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
+ if (find < rates[i])
+ break;
+
+ if (WARN_ON(i == 0))
+ return 0;
+
+ return i - 1;
+}
+
static int intel_dp_common_rates(struct intel_dp *intel_dp,
int *common_rates)
{
@@ -1382,6 +1402,9 @@ static int intel_dp_common_rates(struct intel_dp *intel_dp,
sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
source_len = intel_dp_source_rates(intel_dp, &source_rates);
+ if (i915.max_port_clock > 0)
+ source_len = rate_to_index(i915.max_port_clock, source_rates) + 1;
+
return intersect_rates(source_rates, source_len,
sink_rates, sink_len,
common_rates);
@@ -1426,20 +1449,6 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("common rates: %s\n", str);
}
-static int rate_to_index(int find, const int *rates)
-{
- int i = 0;
-
- for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
- if (find < rates[i])
- break;
-
- if (WARN_ON(i == 0))
- return 0;
-
- return i - 1;
-}
-
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 629337dbca3d..7fe169ed3e49 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -354,6 +354,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
{
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ if (i915.max_dot_clock)
+ max_dotclk = min(i915.max_dot_clock, max_dotclk);
+
/* TODO - validate mode against available PBN for link */
if (mode->clock < 10000)
return MODE_CLOCK_LOW;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index de8e9fb51595..3f4abac8ea4c 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -985,6 +985,9 @@ intel_dsi_mode_valid(struct drm_connector *connector,
const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ if (i915.max_dot_clock)
+ max_dotclk = min(i915.max_dot_clock, max_dotclk);
+
DRM_DEBUG_KMS("\n");
if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 47bdf9dad0d3..6cec78957be0 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -214,6 +214,9 @@ intel_dvo_mode_valid(struct drm_connector *connector,
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
int target_clock = mode->clock;
+ if (i915.max_dot_clock)
+ max_dotclk = min(i915.max_dot_clock, max_dotclk);
+
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 4df9f384910c..74ec74a084fc 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1203,6 +1203,9 @@ static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
struct drm_device *dev = intel_hdmi_to_dev(hdmi);
int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
+ if (i915.max_port_clock)
+ max_tmds_clock = min(i915.max_port_clock, max_tmds_clock);
+
if (respect_downstream_limits) {
if (hdmi->dp_dual_mode.max_tmds_clock)
max_tmds_clock = min(max_tmds_clock,
@@ -1246,6 +1249,9 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
int clock;
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ if (i915.max_dot_clock)
+ max_dotclk = min(i915.max_dot_clock, max_dotclk);
+
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 49550470483e..4df7a53d27db 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -293,6 +293,9 @@ intel_lvds_mode_valid(struct drm_connector *connector,
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
+ if (i915.max_dot_clock)
+ max_pixclk = min(i915.max_dot_clock, max_pixclk);
+
if (mode->hdisplay > fixed_mode->hdisplay)
return MODE_PANEL;
if (mode->vdisplay > fixed_mode->vdisplay)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index e378f35365a2..4f5af6ff1f42 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1527,6 +1527,9 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ if (i915.max_dot_clock)
+ max_dotclk = min(i915.max_dot_clock, max_dotclk);
+
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 49136ad5473e..f282a7c3633d 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -887,6 +887,9 @@ intel_tv_mode_valid(struct drm_connector *connector,
const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ if (i915.max_dot_clock)
+ max_dotclk = min(i915.max_dot_clock, max_dotclk);
+
if (mode->clock > max_dotclk)
return MODE_CLOCK_HIGH;
--
2.7.4
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