Currently on GEN9 if multiple outputs are disabled atomically we'll program the disabled watermark and DDB values for the 2nd, 3rd pipe to be disabled too early while the pipes are still active. Fix this by updating the watermark and DDB values only after all the selected pipes are disabled already. This fixed FIFO underflows during suspend to ram and disk on my BXT. CC: Matt Roper <matthew.d.roper@xxxxxxxxx> CC: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=96914 Reference: https://bugs.freedesktop.org/show_bug.cgi?id=96915 Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_display.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 78beb7e..3c0c2d6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13682,12 +13682,14 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) */ intel_check_cpu_fifo_underruns(dev_priv); intel_check_pch_fifo_underruns(dev_priv); - - if (!crtc->state->active) - intel_update_watermarks(crtc); } } + for_each_crtc_in_state(state, crtc, old_crtc_state, i) { + if (needs_modeset(crtc->state) && !crtc->state->active) + intel_update_watermarks(crtc); + } + /* Only after disabling all output pipelines that will be changed can we * update the the output configuration. */ intel_modeset_update_crtc_state(state); -- 2.5.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
