On Tue, Jul 19, 2016 at 11:25:29AM +0100, Peter Antoine wrote:
> On some platforms the MOCS values are not always saved and restored
> on RC6 enter/exit. The rational is that the context with restore
> these values. On these platforms the test will fail as it tests the
> values by directly reading the MOCS registers.
But there's nothing wrong with the existing tests per-se? You just want
to add a new one that explicitly tests rc6 save/restore, and in doing so
just need to limit the forcewake. For that you just want to limit
intel_register_access to the critical sections. (You don't need to find
the pci_dev afresh everytime.)
> +static unsigned int readit(const char *path)
> +{
> + unsigned int ret = 0;
> + int scanned = 0;
> + FILE *file;
> +
> + file = fopen(path, "r");
> + igt_assert(file);
> + scanned = fscanf(file, "%u", &ret);
> + igt_assert_eq(scanned, 1);
> +
> + fclose(file);
> +
> + return ret;
> +}
> +
> +static int read_rc6_residency(void)
> +{
> + unsigned int residency;
> + const int device = drm_get_card();
> + static const char path_format[] =
> + "/sys/class/drm/card%d/power/rc6_residency_ms";
> + char path[sizeof(path_format)];
> + int ret;
> +
> + ret = snprintf(path, sizeof(path)-1, path_format, device);
> +
> + igt_assert_neq(ret, -1);
> + residency = readit(path);
This should be using a sysfs helper. igt_sysfs.c should already be
sufficient, or if not, please improve.
> + return residency;
> +}
> +
> +static void context_rc6_test(void)
> +{
> + int fd = drm_open_driver(DRIVER_INTEL);
> + int res_ms;
> + uint32_t ctx_id = gem_context_create(fd);
> +
> + igt_debug("RC6 Context Test\n");
> + check_control_registers(fd, I915_EXEC_RENDER, ctx_id, false);
> + check_l3cc_registers(fd, I915_EXEC_RENDER, ctx_id, false);
> +
> + res_ms = read_rc6_residency();
> + sleep(3);
And you could spin here until rc6 residency increased.
timeout = 3000 / 2;
while (read_rc6_residency() == initial_res && --timeout)
usleep(2000);
and importantly: igt_require(read_rc6_residency() != initial_res);
Don't assert for what may be a user configuration.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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