Moving all GPU features to the platform struct definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumping struct
definitions
Signed-off-by: Carlos Santa <carlos.santa@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26283b5..a58765b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -779,6 +779,7 @@ struct intel_csr {
func(has_rc6p) sep \
func(has_dp_mst) sep \
func(has_aux_irq) sep \
+ func(has_gmbus_irq) sep \
func(has_resource_streamer) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
@@ -2837,7 +2838,7 @@ struct drm_i915_cmd_table {
* interrupt source and so prevents the other device from working properly.
*/
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->has_aux_irq)
-#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
+#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9a5cb33..4652e2d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -181,6 +181,7 @@ static const struct intel_device_info intel_pineview_info = {
.gen = 5, .num_pipes = 2, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.has_aux_irq = 1, \
+ .has_gmbus_irq = 1, \
.ring_mask = RENDER_RING | BSD_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -205,6 +206,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
.has_rc6 = 1, \
.has_rc6p = 1, \
.has_aux_irq = 1, \
+ .has_gmbus_irq = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -226,6 +228,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
.has_core_ring_freq = 1, \
.has_rc6 = 1, \
.has_aux_irq = 1, \
+ .has_gmbus_irq = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -260,6 +263,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
.has_runtime_pm = 1, \
.has_rc6 = 1, \
.has_aux_irq = 1, \
+ .has_gmbus_irq = 1, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -339,6 +343,7 @@ static const struct intel_device_info intel_cherryview_info = {
.has_rc6 = 1,
.has_dp_mst = 1,
.has_aux_irq = 1,
+ .has_gmbus_irq = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -379,6 +384,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_resource_streamer = 1,
.has_rc6 = 1,
.has_aux_irq = 1,
+ .has_gmbus_irq = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
