On Wed, Jul 13, 2016 at 04:32:03PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Bspec tells us to keep bashing the PCU for up to 3ms when trying to
> inform it about an upcoming change in the cdclk frequency. Currently
> we only keep at it for 15*10usec (+ whatever delays gets added by
> the sandybridge_pcode_read() itself). Let's change the limit to 3ms.
>
> I decided to keep 10 usec delay per iteration for now, even though
> the spec doesn't really tell us to do that.
>
> Cc: David Weinehall <david.weinehall@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
I've been using this patch for two weeks now on both of my Skylake
machines without any problems. Without this patch I've managed to
trigger:
"[drm:skl_set_cdclk [i915]] *ERROR* failed to inform PCU about cdclk
change"
Tested-by: David Weinehall <david.weinehall@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 +---------
> 1 file changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index be3b2cab2640..90f26f0e2571 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5691,15 +5691,7 @@ static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
>
> static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
> {
> - unsigned int i;
> -
> - for (i = 0; i < 15; i++) {
> - if (skl_cdclk_pcu_ready(dev_priv))
> - return true;
> - udelay(10);
> - }
> -
> - return false;
> + return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
> }
>
> static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
> --
> 2.7.4
>
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