On Tue, Jul 12, 2016 at 05:47:02PM +0100, Chris Wilson wrote:
> On Tue, Jul 12, 2016 at 07:24:47PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > Prior to gen6 we didn't have per-ring IMR registers, which means that
> > since commit 61ff75ac20ff ("drm/i915: Simplify enabling
> > user-interrupts with L3-remapping") we're now masking off all interrupts
> > when init_render_ring() gets called.
>
> That confused me, we're just writing to a non-existent register, so it
> shouldn't have any effect.
RING_IMR(RCS) == 0x20a8 == IMR
>
> > That's rather rude. Let's limit
> > the ring IMR frobbing to machines that actually have the per-ring IMR
> > registers.
> >
> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> > Fixes: 61ff75ac20ff ("drm/i915: Simplify enabling user-interrupts with L3-remapping")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Reviewd-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
>
> Did you see anything to cause concern? I've run this patch on gen2-9, so
> I wonder what I missed and how.
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Ville Syrjälä
Intel OTC
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