On Fri, Jun 24, 2016 at 02:07:14PM +0100, Chris Wilson wrote: > One of the numerous VT-d workarounds we require is that the display > hardware reads past the end of the buffer triggering VT-d faults. This > is acknowledged in the code as being safe "since we fill the unused > portions of the GGTT with the scratch page". Alas, that is no longer > always true and so we trigger DMAR read faults. > > Skylake also requires another workaround to avoid mixing VT-d and > unpopulated PTE, and so there we also need to ensure we fill unused > entries with the scratch page. > > Reported-by: Mike Lothian <mike@xxxxxxxxxxxxxx> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96584 > Fixes: f7770bfd9fd2 ("drm/i915: Skip clearing the GGTT on full-ppgtt systems") > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: David Weinehall <david.weinehall@xxxxxxxxx> > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> Ping? -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
