On Wed, Jul 06, 2016 at 03:30:11PM +0100, Dave Gordon wrote: > Rather than using wait_for_atomic() when chacking for a response from > the GuC, we can get the effect of a hybrid spin/sleep wait by breaking > it into two stages. First, spin-wait for up to 10us to minimise latency > for "quick" commands; then, if that times out, sleep-wait for up 10ms > (the maximum allowed for a "slow" command). > > Being able to do this depends on the recent patch > 18f4b84 drm/i915: Use atomic waits for short non-atomic ones > and is similar to the hybrid approach in > 1758b90 drm/i915: Use a hybrid scheme for fast register waits > (although we can't use that as-is, because that interface doesn't quite > match what we need here). Returning the status from wait_for_register would help for one other callsite (gmbus iirc), not worth the conversion. > Signed-off-by: Dave Gordon <david.s.gordon@xxxxxxxxx> > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> This entire sequence is under the FORCEWAKE_ALL (from inspection of intel_uncore, I think you only need FORCEWAKE_BLITTER), you could use I915_WRITE_FW / I915_READ_FW here - you lose both the spinlock and auto-arming on each read, but you also lose the mmiotracing. (Though realistically we should use the general mmiotracer and fix it if it doesn't work for us.) -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
