HW revision is mandatory field for DisplayPort branch devices. This is defined in DPCD register field 0x509. Signed-off-by: Mika Kahola <mika.kahola@xxxxxxxxx> --- drivers/gpu/drm/drm_dp_helper.c | 21 +++++++++++++++++++++ include/drm/drm_dp_helper.h | 7 +++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 4003464..cfd75df 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -514,6 +514,27 @@ int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], EXPORT_SYMBOL(drm_dp_downstream_max_bpc); /** + * drm_dp_downstream_hw_rev() - read DP branch device HW revision + * @aux: DisplayPort AUX channel + * + * Returns HW revision on succes or negative error code on failure + */ +struct drm_dp_revision drm_dp_downstream_hw_rev(struct drm_dp_aux *aux) +{ + uint8_t tmp; + struct drm_dp_revision rev = { .major = -EINVAL, .minor = -EINVAL }; + + if (drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &tmp, 1) != 1) + return rev; + + rev.major = (tmp & 0xf0) >> 4; + rev.minor = tmp & 0xf; + + return rev; +} +EXPORT_SYMBOL(drm_dp_downstream_hw_rev); + +/** * drm_dp_downstream_id() - identify branch device * @aux: DisplayPort AUX channel * diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8264d54..5f577e4 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -446,6 +446,7 @@ #define DP_SINK_OUI 0x400 #define DP_BRANCH_OUI 0x500 #define DP_BRANCH_ID 0x503 +#define DP_BRANCH_HW_REV 0x509 #define DP_SET_POWER 0x600 # define DP_SET_POWER_D0 0x1 @@ -803,6 +804,11 @@ struct drm_dp_link { unsigned long capabilities; }; +struct drm_dp_revision { + int major; + int minor; +}; + int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); @@ -812,6 +818,7 @@ int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]); int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); +struct drm_dp_revision drm_dp_downstream_hw_rev(struct drm_dp_aux *aux); void drm_dp_aux_init(struct drm_dp_aux *aux); int drm_dp_aux_register(struct drm_dp_aux *aux); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx