On Tue, Jul 05, 2016 at 12:45:55PM +0100, Chris Wilson wrote:
> Following on from the scenario Tvrtko envision to explain a hard-to-hit
> race with multiple first waiters, we could also then race in the
> __i915_request_irq_complete() and the bottom-half may miss the vital
> irq-seqno barrier and so go to sleep not noticing their seqno is
> complete.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c269e0a..9a5498c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3999,6 +3999,8 @@ static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
> */
> if (engine->irq_seqno_barrier &&
> cmpxchg_relaxed(&engine->irq_posted, 1, 0)) {
> + struct task_struct *tsk;
> +
> /* The ordering of irq_posted versus applying the barrier
> * is crucial. The clearing of the current irq_posted must
> * be visible before we perform the barrier operation,
> @@ -4012,6 +4014,24 @@ static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
> * seqno update.
> */
> engine->irq_seqno_barrier(engine);
> +
> + /* If we consume the irq, but we are no longer the bottom-half,
> + * the real bottom-half may not have serialised their own
> + * seqno check with the irq-barrier (i.e. may have inspected
> + * the seqno before we believe it coherent).
> + */
> + rcu_read_lock();
> + tsk = READ_ONCE(engine->breadcrumbs.tasklet);
> + if (tsk != current)
> + /* Note that if the bottom-half is changed as we
> + * are sending the wake-up, the new bottom-half will
> + * be woken by whomever made the change. We only have
> + * to worry about when we steal the irq-posted for
> + * ourself.
> + */
> + wake_up_process(tsk);
> + rcu_read_lock();
Please pretend that I wrote rcu_read_unlock(). Thankyou.
-Chris
>
--
Chris Wilson, Intel Open Source Technology Centre
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