Tim Gore Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ > -----Original Message----- > From: Chris Wilson [mailto:chris.ickle.wilson@xxxxxxxxx] On Behalf Of Chris > Wilson > Sent: Tuesday, July 05, 2016 10:08 AM > To: Gore, Tim > Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: Re: [PATCH v2] drm/i915:gen9: implement > WaMediaPoolStateCmdInWABB > > On Tue, Jul 05, 2016 at 10:01:30AM +0100, tim.gore@xxxxxxxxx wrote: > > From: Tim Gore <tim.gore@xxxxxxxxx> > > > > This patch applies WaMediaPoolStateCmdInWABB which fixes a problem > > with the restoration of thread counts on resuming from RC6. > > > > References: HSD#2137167 > > Signed-off-by: Tim Gore <tim.gore@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/intel_lrc.c | 25 +++++++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > > b/drivers/gpu/drm/i915/intel_lrc.c > > index 676b532..017b25c 100644 > > --- a/drivers/gpu/drm/i915/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/intel_lrc.c > > @@ -1296,6 +1296,31 @@ static int gen9_init_indirectctx_bb(struct > intel_engine_cs *engine, > > wa_ctx_emit(batch, index, 0); > > wa_ctx_emit(batch, index, 0); > > } > > + > > + /* WaMediaPoolStateCmdInWABB:bxt */ > > + if (HAS_POOLED_EU(engine->i915)) { > > + /* > > + * EU pool configuration is setup along with golden context > > + * during context initialization. > > And then mention why we need it per-bb. > > "...The EU pool however needs to be re-enabled following rc6." > > So what happens when the device goes into rc6 in the middle of a batch? > -Chris > As I understand it from the email thread attached to the HSD, this workaround is for exactly the case when we enter RC6 mid batch. When we resume, the pooled eu mode is restored BUT this happens after the thread counts are restored, leading to corruption of the thread counts. This workaround forces the pooled eu mode to get "restored" (re-initialised really) before the thread counts. Tim > -- > Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
