Ok, so I generally try to avoid MIME-encoded emails because my old legacy
tools didn't handle them, but since 'git am' is supposed to be able to
handle them, I just tried one. And it failed.
Un-encoding them in the email client and then re-doing the thing worked
fine, so it's definitely related to the MIME-decoding somehow.
I'm attaching both versions of the email so people can test it out (it
applies to v2.6.26-rc9 of the kernel), but the behaviour in short is that
the plain version (ie the one where I used my MUA to "export" the email
without MIME crud) results in the correct:
commit 97f8571e663c808ad2d01a396627235167291556
Author: Philipp Zabel <philipp.zabel@xxxxxxxxx>
Date: Sun Jul 6 01:15:34 2008 +0200
pxamci: fix byte aligned DMA transfers
The pxa27x DMA controller defaults to 64-bit alignment. This caused
the SCR reads to fail (and, depending on card type, error out) when
card->raw_scr was not aligned on a 8-byte boundary.
...
while the MIME-encoded version results in
commit 92cdd47753abc9a6f1b8d96fedcbb5ed88b5ab57
Author: Pierre Ossman <drzeus-list@xxxxxxxxx>
Date: Sun Jul 6 01:15:34 2008 +0200
pxamci: fix byte aligned DMA transfers
F
The pxa27x DMA controller defaults to 64-bit alignment. This caused
the SCR reads to fail (and, depending on card type, error out) when
card->raw_scr was not aligned on a 8-byte boundary.
...
ie notice how the "From: Philipp Zabel <philipp.zabel@xxxxxxxxx>" got
corrupted somehow. It was apparently _partially_ recognized and removed,
but it left the 'F' around, and probably because of the partial removal it
then didn't get recognized as the author, so the original email sender
(Pierre) got credit.
This is with a git version as of five minutes ago: v1.5.6.2-220-g44701c6.
Any ideas? I have not looked at it at all, since I'm not a fan of MIME,
and didn't have anything to do with the MIME-decoding code.
Linus
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Date: Sun, 6 Jul 2008 01:15:34 +0200
From: Pierre Ossman <drzeus-list@xxxxxxxxx>
To: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
Cc: LKML <linux-kernel@xxxxxxxxxxxxxxx>,
Philipp Zabel <philipp.zabel@xxxxxxxxx>,
Stable branch <stable@xxxxxxxxxx>
Subject: [PATCH] pxamci: fix byte aligned DMA transfers
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From: Philipp Zabel <philipp.zabel@xxxxxxxxx>
The pxa27x DMA controller defaults to 64-bit alignment. This caused
the SCR reads to fail (and, depending on card type, error out) when
card->raw_scr was not aligned on a 8-byte boundary.
For performance reasons all scatter-gather addresses passed to
pxamci_request should be aligned on 8-byte boundaries, but if
this can't be guaranteed, byte aligned DMA transfers in the
have to be enabled in the controller to get correct behaviour.
Signed-off-by: Philipp Zabel <philipp.zabel@xxxxxxxxx>
Signed-off-by: Pierre Ossman <drzeus@xxxxxxxxx>
---
drivers/mmc/host/pxamci.c | 13 +++++++++++++
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 65210fc..d89475d 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -114,6 +114,7 @@ static void pxamci_setup_data(struct pxamci_host *host,=
struct mmc_data *data)
unsigned int nob =3D data->blocks;
unsigned long long clks;
unsigned int timeout;
+ bool dalgn =3D 0;
u32 dcmd;
int i;
=20
@@ -152,6 +153,9 @@ static void pxamci_setup_data(struct pxamci_host *host,=
struct mmc_data *data)
host->sg_cpu[i].dcmd =3D dcmd | length;
if (length & 31 && !(data->flags & MMC_DATA_READ))
host->sg_cpu[i].dcmd |=3D DCMD_ENDIRQEN;
+ /* Not aligned to 8-byte boundary? */
+ if (sg_dma_address(&data->sg[i]) & 0x7)
+ dalgn =3D 1;
if (data->flags & MMC_DATA_READ) {
host->sg_cpu[i].dsadr =3D host->res->start + MMC_RXFIFO;
host->sg_cpu[i].dtadr =3D sg_dma_address(&data->sg[i]);
@@ -165,6 +169,15 @@ static void pxamci_setup_data(struct pxamci_host *host=
, struct mmc_data *data)
host->sg_cpu[host->dma_len - 1].ddadr =3D DDADR_STOP;
wmb();
=20
+ /*
+ * The PXA27x DMA controller encounters overhead when working with
+ * unaligned (to 8-byte boundaries) data, so switch on byte alignment
+ * mode only if we have unaligned data.
+ */
+ if (dalgn)
+ DALGN |=3D (1 << host->dma);
+ else
+ DALGN &=3D (1 << host->dma);
DDADR(host->dma) =3D host->sg_dma;
DCSR(host->dma) =3D DCSR_RUN;
}
--=20
-- Pierre Ossman
Linux kernel, MMC maintainer http://www.kernel.org
rdesktop, core developer http://www.rdesktop.org
WARNING: This correspondence is being monitored by the
Swedish government. Make sure your server uses encryption
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From drzeus-list@xxxxxxxxx Sat Jul 5 16:17:53 2008
Date: Sun, 6 Jul 2008 01:15:34 +0200
From: Pierre Ossman <drzeus-list@xxxxxxxxx>
To: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
Cc: LKML <linux-kernel@xxxxxxxxxxxxxxx>, Philipp Zabel <philipp.zabel@xxxxxxxxx>, Stable branch <stable@xxxxxxxxxx>
Subject: [PATCH] pxamci: fix byte aligned DMA transfers
From: Philipp Zabel <philipp.zabel@xxxxxxxxx>
The pxa27x DMA controller defaults to 64-bit alignment. This caused
the SCR reads to fail (and, depending on card type, error out) when
card->raw_scr was not aligned on a 8-byte boundary.
For performance reasons all scatter-gather addresses passed to
pxamci_request should be aligned on 8-byte boundaries, but if
this can't be guaranteed, byte aligned DMA transfers in the
have to be enabled in the controller to get correct behaviour.
Signed-off-by: Philipp Zabel <philipp.zabel@xxxxxxxxx>
Signed-off-by: Pierre Ossman <drzeus@xxxxxxxxx>
---
drivers/mmc/host/pxamci.c | 13 +++++++++++++
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 65210fc..d89475d 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -114,6 +114,7 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
unsigned int nob = data->blocks;
unsigned long long clks;
unsigned int timeout;
+ bool dalgn = 0;
u32 dcmd;
int i;
@@ -152,6 +153,9 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
host->sg_cpu[i].dcmd = dcmd | length;
if (length & 31 && !(data->flags & MMC_DATA_READ))
host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN;
+ /* Not aligned to 8-byte boundary? */
+ if (sg_dma_address(&data->sg[i]) & 0x7)
+ dalgn = 1;
if (data->flags & MMC_DATA_READ) {
host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
@@ -165,6 +169,15 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
wmb();
+ /*
+ * The PXA27x DMA controller encounters overhead when working with
+ * unaligned (to 8-byte boundaries) data, so switch on byte alignment
+ * mode only if we have unaligned data.
+ */
+ if (dalgn)
+ DALGN |= (1 << host->dma);
+ else
+ DALGN &= (1 << host->dma);
DDADR(host->dma) = host->sg_dma;
DCSR(host->dma) = DCSR_RUN;
}
--
-- Pierre Ossman
Linux kernel, MMC maintainer http://www.kernel.org
rdesktop, core developer http://www.rdesktop.org
WARNING: This correspondence is being monitored by the
Swedish government. Make sure your server uses encryption
for SMTP traffic and consider using PGP for end-to-end
encryption.
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