Hello David, Actually I was following this video: https://www.youtube.com/watch?v=RT0GqJySnBc to add custom float instructions to risc-v, as per the video one has to modify riscv-opc.c, riscv-opc.h and riscv.md. I added fsin instruction by defining match, mask in the file riscv-opc.h, fsin.s to riscv-opc.c, I did define instruction in riscv-gcc/gcc/config/riscv/riscv.md as shown below (define_insn "sin<mode>2" [(set (match_operand:ANYF 0 "register_operand" "=f") (sin:ANYF (match_operand:ANYF 1 "register_operand" " f")))] "TARGET_HARD_FLOAT && TARGET_FDIV" { return "fsin.<fmt>\t%0,%1"; } [(set_attr "type" "fsin") (set_attr "mode" "<UNITMODE>")]) when I configure and make I am getting following error: ../.././riscv-gcc/gcc/config/riscv/riscv.md:838:12: error: unknown rtx code sin' ../.././riscv-gcc/gcc/config/riscv/riscv.md:838:67: note: following context is :ANYF (match_operand:ANYF 1 "register_operand" " f")))]' make[2]: *** [s-preds-h] Error 1 make[2]: *** Waiting for unfinished jobs.... ../.././riscv-gcc/gcc/config/riscv/riscv.md:838:12: error: unknown rtx code sin' ../.././riscv-gcc/gcc/config/riscv/riscv.md:838:67: note: following context is :ANYF (match_operand:ANYF 1 "register_operand" " f")))]' make[2]: *** [s-conditions] Error 1 ../.././riscv-gcc/gcc/config/riscv/riscv.md:838:12: error: unknown rtx code sin' ../.././riscv-gcc/gcc/config/riscv/riscv.md:838:67: note: following context is :ANYF (match_operand:ANYF 1 "register_operand" " f")))]' ../.././riscv-gcc/gcc/config/riscv/riscv.md:838:12: error: unknown rtx code sin' ../.././riscv-gcc/gcc/config/riscv/riscv.md:838:67: note: following context is :ANYF (match_operand:ANYF 1 "register_operand" " f")))]' make[2]: *** [s-preds] Error 1 make[2]: *** [s-constrs-h] Error 1 Any idea why this error? -Amit On Tue, Aug 13, 2024 at 7:53 PM David Brown <david.brown@xxxxxxxxxxxx> wrote: > > Amit, it looks to me like you are talking at cross-purposes. Correct me > if I am wrong, but I am assuming you are writing code as a user, while > Georg-Johann is also giving advice for adding these new instructions to > the compiler, and that might be confusing you. > > If you want the compiler to use your new custom instructions, you have > to tell it about them. Assuming you don't want to modify the compiler, > then inline assembly statements are the way to handle this. These are > compiler extensions, not macros. There is no magical way to get the > pre-compiled standard maths library to suddenly start using your new > custom instructions. > > So you want to write something like this : > > static inline float sin_fast(float x) { > if (__builtin_constant_p(sinf(x)) { > return sinf(x); > } > > float y; > asm(" custom_sin %[src_reg], %[dst_reg]" > : [dst_reg] "=f" (y) > : [src_reg] "f" (x) > ); > return y; > } > > Replace "custom_sin" with the assembly opcode, as recognized by your > assembler. And I have no idea if the ordering of the source and > destination registers is correct for RISC-V. > > > Then use "sin_fast" instead of "sinf" in your code. > > <https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html> > > > David > > > > > On 07/08/2024 12:04, Amit Hiremath wrote: > > Hello Georg-Johann, > > > > Thanks for the clarification. Actually, I do not want to use asm. If I > > write sample c code like this: > > > > #include <math.h> > > #include <stdio.h> > > > > int main() > > { > > float angle1 = 3.1415926; > > printf("sin(3.14) = %.2lf\n", sin(angle1)); > > return 0; > > } > > > > The compiler should emit this instruction to the concerned FPU part in > > RISC-V. Is it possible this way? Since RISC-V does not have instructions > > for sine, cosine, exp, etc. they are taken care of by soft fp libraries. > > I guess I do not need to rename instructions? > > > > Thanks, > > -Amit > > > > On Wed, Aug 7, 2024 at 3:11 PM Georg-Johann Lay <avr@xxxxxxxx> wrote: > > > >> Am 07.08.24 um 08:24 schrieb Amit Hiremath: > >>> Hello, > >>> > >>> I want to add custom single precision floating point sine, cosine, exp > >>> instructions to risc-v gnu tool chain, and I have designed hardware for > >>> this. I was going through tutorials on how to add custom instructions > at: > >>> https://pcotret.gitlab.io/riscv-custom/sw_toolchain.html after adding > >>> custom instructions, I think one has to use asm volatile macro to use > >>> custom instructions in C. Is there anyway where one do not need to use > >> this > >> > >> Hi, There is no need for asm volatile, asm is enough because there are > >> no side effects other than the computation. And for compile-time > >> constants, there is no need for asm, like in: > >> > >> if (__builtin_constant_p (sinf (x)) > >> y = sinf (x); > >> else > >> __asm ("..." : "=r" (y), ...); > >> > >>> macro? I would like the compiler to automatically map to custom > >>> instructions in the risc-v processor, like how it will map to fadd.s, > >>> fmul.s instructions, where one does not need to use asm volatile macro. > >> > >> This would be a new insn named "sinsf2" for sinf. The "sf" stands for > >> SFmode (single float, e.g. IEEE single). > >> > >> https://gcc.gnu.org/onlinedocs/gccint/Standard-Names.html > >> > >> You can have a look at how other backends are doing it, for example > >> grep the GCC sources: > >> > >> $ grep -rn '"sin' gcc/config | grep -v single > >> > >> which yields a dozen or so hits, for example nvptx: > >> > >> (define_insn "sinsf2" > >> [(set (match_operand:SF 0 "nvptx_register_operand" "=R") > >> (unspec:SF [(match_operand:SF 1 "nvptx_register_operand" "R")] > >> UNSPEC_SIN))] > >> "flag_unsafe_math_optimizations" > >> "%.\\tsin.approx%t0\\t%0, %1;") > >> > >> (I don't know whether unspec is still required today. rtl.def > >> doesn't seen to have sin, so yes, you need an unspec.) > >> > >> The insn condition is presumably because the nvptx sinf is not > >> fully IEEE compliant. When sinf is available on some devices > >> but not on others, the insn condition would express that, too. > >> > >> The constraints would be the same like in an asm. When there > >> are no appropriate constraints and the asm is using local > >> register variables, then you'll have to add new register > >> constraints and register classes that describe which > >> hard registers are appropriate for the new instruction. > >> (But notice that there is an upcoming feature that allows > >> single hard register as a constraint like "{r42}".) > >> > >> Finally, as you also have cosf, you would also add insns > >> for cossf2 and sincossf3. > >> > >> HTH > >> > >> Johann > >> > >>> I asked in riscv gnu tool chain forum about this issue: > >>> https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1526 they > >>> suggested that I ask this query in the gcc forum. > >>> > >>> Can you please guide me? > >>> > >>> Many Thanks, > >>> -Amith > >> > > > >
