On Fri, 2023-08-11 at 07:34 -0600, Jeff Law via Gcc-help wrote: > > > On 8/10/23 19:48, Hanchao Li via Gcc-help wrote: > > I am in the process of adapting a chip with the RV32I architecture. > > Due to some issues with SRAM, I cannot use the "sb" instruction and must > > use the "sw" instruction with word alignment. I attempted to replace the > > "store byte" with "store word" in the "riscv_output_move" function in > > "gcc/config/riscv/riscv.c", > > > > switch (GET_MODE_SIZE (mode)) > > case 1: return "sb\t%z1,%0"; > > case 2: return "sh\t%z1,%0"; > > case 4: return "sw\t%z1,%0"; > > case 8: return "sd\t%z1,%0"; > > > > but encountered some difficulties. For example, in "case 1: return > > "sb\t%z1,%0";", "%0" can only be of type "mem", making it difficult to > > align the address using instructions. Is there any feasible method to > > achieve the conversion of "sb" to "sw"? > There's no generic way to do this and it's going to be more complex than > just changing a few opodes and dealing with alignments. > > Don't you have to read in the full word, zero out one byte in the word, > insert the data you want to store at the appropriate byte, then write > out the whole word? Which means you need a scratch register. You're > likely going to have remove that register from the allocatable set so > that you can use it as a scratch. And all of this would be horribly > wrong to do for memory mapped IO. > > There's probably other problems lurking. An example of "other problems": you'll need to use a lr/sc loop for any atomic single-byte store. I guess it's easier to fix the hardware... -- Xi Ruoyao <xry111@xxxxxxxxxxx> School of Aerospace Science and Technology, Xidian University
