On 02/08/2023 11:07, Xingyi Li via Gcc-help wrote:
Hi,
I am using gcc-10.2-arm32-eabi with Cortex-R52 processors. The veneer code inserted by the compiler is possibly wrong.
Take IRQ_Handler for example, the veneer code is like below. The first instruction is bx pc, which always switches CPSR to ARM mode. However, my whole project is using Thumb instructions. Can you please help explain how to make the veneer code right, like adding compiler options?
<__IRQ_Handler_veneer>:
bx pc
b.n 35811fa0 <__IRQ_Handler_veneer>
ldr pc, [pc, #-4]
.word 0x7dac0cfc
this veneer is inserted because of the long distance of the IRQ_handler code.
However, what confuses me is that it also generates the bx instruction, even if with the following related commands:
-mcpu=cortex-r52 ( make sure the CPU is correctly told )
-mthumb ( and there is no -mthumb-interwork )
There's nothing wrong with switching to Arm state on the cortex-R52 - it
has a complete implementation of both the A32 (Arm) and T32 (Thumb)
instruction sets. The reason why this stub does this is because there
is no direct equivalent in Thumb of
ldr pc, [pc, #-4]
and it would take several instructions to synthesize it. This
instruction will load the PC with the value of the next location in
memory, and if that is a 'thumb' address, switch back to T32 state again
(since in armv8-r, 'ldr pc' will support a change back to T32).
So I think your real problem is that the value being loaded (0x7dac0cfc)
is not a thumb address and we need to work out why that is not the case.
> May I ask more about the documentation problem? Since I found no
> veneer-related information in the GCC 10.2 Manual, could you please
> tell me which gcc documents I should refer to?
This is related to the linker and the GCC manual does not cover any of
that (beyond some very basic bits on how to make GCC pass options
through to the linker). Any relevant details would be in the
documentation for the linker (ld).
R.
