On Wed, 2023-04-19 at 23:53 -0700, Matthew R. Wilson wrote: > Hello, > > I'm looking into writing some code for a POWER9 processor in which I > want to explicitly use the VSX scalar instructions for quad-precision > floating point arithmetic. > > In the GCC documentation, section 6.60.22.5, the relevant built-in > functions are listed (see > <https://gcc.gnu.org/onlinedocs/gcc/Basic-PowerPC-Built-in-Functions-Available-on-ISA-3_002e0.html#Basic-PowerPC-Built-in-Functions-Available-on-ISA-3_002e0>) > > However, it looks like only the ..._round_to_odd versions of the > functions exist. But in the Power ISA 3.0, there are both the "normal" > version of the instruction (that use the rounding mode configured in the > floating-point control register, as all of the other floating point > instructions do) and the "round to odd" versions of the instructions. > > (See, for example, the VSX Scalar Add Quad-Precision instruction on page > 520 of the Power ISA Version 3.0 B PDF at > <https://wiki.raptorcs.com/w/images/c/cb/PowerISA_public.v3.0B.pdf>) > > That is, two instructions exist: xsaddqp and xdaddqpo, with the latter > being the round-to-odd version of the instruction. I have verified that > using the GCC __builtin_addf128_round_to_odd function does produce code > that uses xsaddqpo, but it would be more typical to want to generate > code that uses xsaddqp. It seems like an equivalent __builtin_addf128 > function is missing (for add and all of the other quad-precision VSX > scalar arithmetic instructions that have both xxx and xxxo > instructions). > > Is there a particular reason this is the case, or is it indeed just an > oversight? Because you can simply say "a + b": https://godbolt.org/z/6a73xv11b -- Xi Ruoyao <xry111@xxxxxxxxxxx> School of Aerospace Science and Technology, Xidian University
