In this CPU, A multi-cycle instruction, once decoded, runs in parallel as other decoded single/multi-cycle instructions. A single/multi-cycle instruction takes two operands, where the first operand receives the result of computing both operands. An example of multi-cycle instruction is "div". An example of single-cycle instruction is "add". GCC should be able to transform following: ```` add %0 %5 add %1 %6 div %4 %5 #<-- Multi-cycle instruction. add %4 %7 #<-- Next instruction that depends on its result. add %3 %7 add %2 %7 ``` To: ``` div %4 %5 #<-- Multi-cycle instruction. add %0 %5 add %1 %6 add %3 %7 add %2 %7 add %4 %7 #<-- Next instruction that depends on its result. ``` Without above transformation, `add %4 %7` would cause the cpu to wait on `div %4 %5` when it could have executed instructions that do not depend on the result of "div".
