On 1/26/2022 6:20 PM, Reshabh K Sharma via Gcc-help wrote:
Hello everyone,
I am trying to implement a post address update load instruction in our
downstream riscv backend. I want to attach write latency information to a
use register. For example, rd = new_load rs1 rs2, I want to attach separate
write latency information to both rd and rs1.
I am unable to find how to describe instructions that have an operand as
both def and use, and later attach write latency information for the
instruction scheduler to work properly.
It will also be very helpful if you can point me to the implementation of
similar instructions in other backends, for example, LBZU in PowerPC, ARM's
LWD post/pre address update versions and ARM's neon simd load with update.
I'm not sure the scheduler can model different latencies for the
multiple outputs. If anyone knows for sure, it would be Vlad.
It may not matter in practice though. I'd hazard a guess these things
hang out in the reorder buffer until both outputs are ready and only
then will it move into the retirement queue.
jeff
