A simpler question from me should have been: What should a define_constraint look like to match the following operand ? (mem/f/c:SI (mem/c:SI (reg/f:SI 0 %sp))) On Fri, Aug 16, 2019 at 10:36 AM William Tambe <tambewilliam@xxxxxxxxx> wrote: > > Could anyone easily point out what machine description could > match/solve this unrecognizable insn ? > I am encountering the failure when building GCC with C++ support: > > ../../../../../gcc/libstdc++-v3/src/c++98/tree.cc: In function > ‘std::_Rb_tree_node_base* > std::_Rb_tree_rebalance_for_erase(std::_Rb_tree_node_base*, > std::_Rb_tree_node_base&)’: > ../../../../../gcc/libstdc++-v3/src/c++98/tree.cc:444:3: error: > unrecognizable insn: > } > ^ > (insn 1366 1364 446 57 (set (reg:SI 15 %rp) > (mem/f/c:SI (mem/c:SI (reg/f:SI 0 %sp) [12 %sfp+-8 S4 A32]) [3 > _141->_M_left+0 S4 A32])) > "../../../../../gcc/libstdc++-v3/src/c++98/tree.cc":145 -1 > (nil)) > during RTL pass: reload > > > Below is an excerpt from the machine description, which I thought > could match the unrecognizable insn: > > (define_constraint "A" > "Symbolic address" > (ior (and (match_code "mem") > (ior (match_test "GET_CODE (XEXP (op, 0)) == SYMBOL_REF") > (match_test "GET_CODE (XEXP (op, 0)) == LABEL_REF") > (match_test "GET_CODE (XEXP (op, 0)) == CONST"))) > (match_code "symbol_ref,label_ref") > (and (match_code "const") > (match_test "GET_CODE (XEXP (op, 0)) == PLUS && > (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF || > GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF) && > CONST_INT_P (XEXP (XEXP (op, 0), 1))")))) > > (define_constraint "W" > "Register indirect memory operand" > (and (match_code "mem") > (match_test "REG_P (XEXP (op, 0))"))) > > (define_constraint "O" > "Constant zero" > (and (match_code "const_int") > (match_test "ival == 0"))) > > (define_insn "movsi" > [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,W,r,A") > (match_operand:SI 1 "general_operand" " O,r,A,i,r,W,r"))] > "" > "@ > li8 %0, 0 > cpy %0, %1 > gip %0, %1 > li %0, %1 > st32 %1, %0 > ld32 %0, %1 > gip %%sr, %0; st32 %1, %%sr")