Hi all, I am trying to understand how the target specifications are used in GCC architecture. I am trying to know how the memory fences get added for power architecture. Are they added after the final RTL pass or the barrier instruction in the IR-RTL gets converted into one? Also, in which phase we identify that the instruction involves some memory ordering for a particular target and we need to give some memory fencing for it, i.e., during GIMPLE to RTL, RTL to RTL or RTL to assembly or somewhere else? Thanks, Akshat
