On 18/03/2019 15:29, Segher Boessenkool wrote: > On Mon, Mar 18, 2019 at 12:09:01PM +0100, David Brown wrote: >> Assuming my memory is correct, of course, it means there is no >> difference between "mftb r6" and "mfspr r6, 284", or between "mftbu r5" >> and "mfspr r5, 285". >> >> However, I think the particular SPR numbers may vary between PPC cores - >> earlier I saw 268 and 269 from a google search, while some old code of >> mine has 284 and 285. So you should prefer to write "mftb" and "mftbu" >> in your souce code, and let the compiler and assembler turn it into the >> correct SPR values for your chip. >> >> But don't worry if you see the mfspr instructions in the disassembly. > > The bit with value 16 in SPR numbers means it is privileged access (*) > (hypervisor, or supervisor on CPUs without hypervisor). You need to write > "mtspr rX,284" to write to the time base. Reading should use 268 (and > this is used with the extended mnemonic mftb; and there is no mttb extended > mnemonic: there used to be mttbl and mttbu extended mnemonics, using 284 > resp. 285, but you are supposed to use mtspr now, and privileged code can > be expected to change faster). > Ah, OK. The PPC stuff I have done is all single-program unhosted embedded code, which runs in privileged mode all the time, and it was a good many years ago. Thank you for filling in the details in this thread, and correcting my errors. (And of course, thanks for your work on the PPC target for gcc!) mvh., David
