On Mon, Mar 18, 2019 at 07:55:00AM +0200, ilya german wrote: > I wrote the following asm instructions to read the TBR: > > mftbu r5 /* Read upper Time Base */ > mftb r6 /* Read lower Time Base */ > mftbu r7 /* Read upper Time Base again */ > > When I compiled (using GNU 4) and viewed the asm instruction I saw that > *mftbu* and *mftb* were replaced with *mfspr* instruction. Please show the exact disassembly (just those insns is enough). Please show the exact GCC and binutils versions. > After search in the documentations I found in: EREF 2.0: A Programmer’s > Reference Manual for Freescale Power Arch Processors (P.504), The following > note "mftb was part of the original PowerPc arch, but is being phased out > of PowerISA...." Yes. There still is an "mftb" instruction, but "mfspr rX,268" and "mfspr rX,269" are preferred. Many assemblers translate to those two for the extended mnemonics "mftb rX" and "mftbu rX". The mftb insn is phased out in ISA 2.03. If you assemble with e.g. -mpower4 you get the mfspr version, instead. > How did the GNU compiler knew that it should replace the obsolete > instruction ? If it is targeting Power4 or later it uses the mfspr form. https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/rs6000/rs6000.md;h=584b9da6e7174eec191ad0aeb3bfd485b7313667;hb=HEAD#l13387 ("TARGET_MFCRF" means Power4 or later). > did PPC deliberately added a patch to make the complier make > those changes ? Yes. > should i worry that the compiler can change explicitly > written asm instructions ? No. The compiler only does this for CPUs where this works as desired. > *And the most important question, is there a flag I can use to explicitly > prevent those changes from happening ?* Use -mcpu=603 (or whatever CPU you actually have / want to target). Segher
