(Please don't top-post.) On 18/03/2019 12:33, ilya german wrote: > The code works as expected. > > I’m working on embedded systems and worry that my specific asm instructions could be changed. > Inline assembly instructions won't be changed. The actual assembly can be moved around, duplicated or omitted by the optimiser if it is not marked "volatile" - but that's okay, it is what you want the compiler to do. > Is there a flag to fail compilation every time the generated instruction won’t match the specified ? The compiler passes inline assembly through to the assembler without modification - compilation does not change the code. The assembler (and occasionally even the linker) may make certain changes, for some target processors - improving branch and jump instruction efficiency springs to mind. But you have to realise that neither the compiler nor the assembler is changing anything here. "mftb" is not an instruction in its own right on most PPC cores (I think it exists on some older ones, and perhaps on the Power architecture, but you'd have to check with someone more knowledgeable than I). It is a pseudo-mnemonic - a name that the assembler interprets to mean the appropriate "mfspr" instruction. The PPC has many such simplified mnemonic. For example, if you try to implement "x = y - 15" using "subi r1, r2, 15", then look at the disassembly, you will see "addi r1, r2, 0xfffffff0". There is no "subtract immediate" instruction on the PPC - but since such a mnemonic would be useful, it is simulated this way. mvh., David > > Ilya German > >> On 18 Mar 2019, at 13:09, David Brown <david@xxxxxxxxxxxxxxx> wrote: >> >>> On 18/03/2019 12:00, ilya german wrote: >>> >>> Can i understand from the answer that asm instructions (not >>> mnemonics) won't be replaced ? >> >> Assuming my memory is correct, of course, it means there is no >> difference between "mftb r6" and "mfspr r6, 284", or between "mftbu r5" >> and "mfspr r5, 285". >> >> However, I think the particular SPR numbers may vary between PPC cores - >> earlier I saw 268 and 269 from a google search, while some old code of >> mine has 284 and 285. So you should prefer to write "mftb" and "mftbu" >> in your souce code, and let the compiler and assembler turn it into the >> correct SPR values for your chip. >> >> But don't worry if you see the mfspr instructions in the disassembly. >> >> And test your code - it should quickly be apparent whether it works or not. >> >> mvh., >> >> David >> >> >>> >>> On Mon, Mar 18, 2019 at 12:22 PM David Brown <david@xxxxxxxxxxxxxxx >>> <mailto:david@xxxxxxxxxxxxxxx>> wrote: >>> >>>> On 18/03/2019 10:08, Florian Weimer wrote: >>>> * ilya german: >>>> >>>>> I have a quastion regarding reading TBR registers on PPC p2020 >>> e500v2 CPU. >>>>> >>>>> I wrote the following asm instructions to read the TBR: >>>>> >>>>> mftbu r5 /* Read upper Time Base */ >>>>> mftb r6 /* Read lower Time Base */ >>>>> mftbu r7 /* Read upper Time Base again */ >>>>> >>>>> When I compiled (using GNU 4) and viewed the asm instruction I >>> saw that >>>>> *mftbu* and *mftb* were replaced with *mfspr* instruction. >>>> >>>> How did you determine that it was replaced? >>>> >>> >>> I expect he could see it from looking at a disassembly. >>> >>> On The PPC cores, mftb and mftbu are simplified mnemonics, not >>> instructions - they are implemented as "mfspr" instructions on the >>> appropriate SPR registers (268 and 269). >>> >>
