On 28.01.2018 14:32, Sébastien Michelland wrote:
Hello,
I am trying to generate a call to the SH-4A unaligned move "movua.l
@rm+, r0" instruction. Currently my inline-assembly approach using
the '>' constraint is rejected by the compiler:
#include <stdint.h>
void f(void)
{
uint32_t longword, *src;
__asm__(
"movua.l %1, %0"
: "=z" (longword)
: ">" (src)
);
}
% sh3eb-elf-gcc -S movua.c -o movua.s -ffreestanding
movua.c: In function 'f':
movua.c:6:2: warning: asm operand 1 probably doesn't match constraints
__asm__(
^~~~~~~
movua.c:6:2: error: impossible constraint in 'asm'
I have tried a lot of variations to no avail.
Am I using the '>' constraint the wrong way? What would be the proper
way to generate this instruction?
A different approach is to explicitly use post-increment if that's the
favourable addressing mode:
__asm__ ("movua.l %1, @%0+"
: "=z" (longword), "+r" (src)
: "m" (*src)
The "+r" (src) constraint tells gcc that src is changed in some way and
is input /and/ output. I am actually not familiar with this specific
architecture, so you might need a different register class to constrain
to valid address register(s).
The "m" (*src) tells gcc that 4 bytes are being red from *src, and there
is no need for "%2" to occur in the asm string.
Johann
