gcc porting: how to generate floating point multiply-add instruction?

[David Kang <dkang@xxxxxxx>]

 Hello,

 The hardware I'm porting gcc onto has floating multiply-add instructions.
I'm trying to make gcc to generate the multiply-add instructions but it doesn't.
I described the instruction in the .md file as follows:

(define_expand "maddsf3"
  [(set (match_operand:SF 0 "register_operand" "")
        (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
                          (match_operand:SF 2 "register_operand" ""))
                 (match_operand:SF 3 "register_operand" "")))]
   ""
   { 
       emit_insn (gen_insn_hw_maddsf(....)); /* details are removed for simple presentation */
       DONE; 
   }
)

 I also tried using define_insn as follows, but it doesn't work, either.

(define_insn "*maddsf3"
  [(set (match_operand:SF 0 "register_operand" "=f")
        (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
                          (match_operand:SF 2 "register_operand" "f"))
                 (match_operand:SF 3 "register_operand" "f")))]
   ""
  "*
   {
       "....."  /* details are removed for simple presentation */
   }
  "
  [(set_attr "..." "...")]  
)

 What am I doing wrong?
I'll appreciate your help.

 David

-- 
----------------------
Dr. Dong-In "David" Kang
Computer Scientist
USC/ISI