The mips backed on gcc defines REG_ALLOC_ORDER to prefer call-clobbered GPRs (t0-t7) over call-saved GPRs (s0-s7). I read that HONOR_REG_ALLOC_ORDER was seen to be beneficial only for selected targets (nds32 and arm) and is not currently defined for the mips target. When there is additional register pressure (I modified some pipeline descriptions to allow multiple issue), I see that HONOR_REG_ALLOC_ORDER helps. When there is no additional register pressure, HONOR_REG_ALLOC_ORDER does no harm. (Disclaimer : This is from a limited set of benchmarks that I have tested ). My question is - REG_ALLOC_ORDER for mips looks reasonably performance oriented, so why isnt HONOR_REG_ALLOC_ORDER defined by fault for this target ? Thanks
