Register spill caused by gcc scheduler?

[Terry Guo <flameroc@xxxxxxxxx>]

Hi there,

I am writing pipeline description for my target and found that a
slight change to description can incur a register spill in reload pass
which then causes performance regression. Is it true that scheduler
can impact the register allocation? If so, what's the best practice to
avoid such case when writing pipeline description? Thanks in advance
for any comments.

BR,
Terry