I am using MIPS32 bit processor(24KEc) with mips16e support. I have a codebase compiled with mips32r2. I need to reduce the code size and hence I am trying to recompile with -mips16. Using GCC 4.8 with -march=mips32r2 -mtune=mips32r2 -mips16 -mips32r2 -minterlink-mips16 compiler options. This gives me the following error while building some of the .so /tmp/cc8ohIfv.s: Assembler messages: /tmp/cc8ohIfv.s:119: Error: unrecognized opcode `wsbh' /tmp/cc8ohIfv.s:119: Error: unrecognized opcode `rotr' If I dont include -mips16 option, assembler dont throw this error and generated the .so successfully. I did an objdump on this .so and verified that it doesnt have wsbh and rotr instructions. So These instructions are generated only when I give -mips16 option and assembler doesn't understand it. As I understand wsbh and rotr are mips32r2 instruction(not in mips16 instruction set) the why compiler generated it in case of mips16? If I include -mips16 along with -mips32r2, does that mean that compiler will generate 16 bit instructions where ever possible and rest will be 32bit instructions(is it similar to thump2 in ARM?)? Is there a way wherein compiler will generate only 16 bit instructions? It looks like I am missing something, please help me to understand better. ~Anoop -- View this message in context: http://gcc.1065356.n5.nabble.com/mips16-compilation-issue-tp1040690.html Sent from the gcc - Help mailing list archive at Nabble.com.
