The problem I have is this:
The following RTL:
(jump_insn 22 21 23 (nil) (parallel [
(set (pc)
(if_then_else (ne (unspec_volatile [
(const_string ("<myinsn> %0,[%1] =%2"))
(const_int 0 [0x0])
(reg/v:SI 343)
] 21)
(const_int 0 [0x0]))
(label_ref:SI 43)
(pc)))
(clobber:SI (reg:SI 321 link))
(set:HI (reg/v:HI 345)
(unspec:HI [
(const_int 0 [0x0])
] 0))
] -1 (nil)
(nil))
(insn 24 23 25 (nil) (set (reg:SI 348)
(plus:SI (reg/v:SI 343)
(const_int 64 [0x40]))) -1 (nil)
(nil))
(jump_insn 25 24 26 (nil) (parallel [
(set (pc)
(if_then_else (ne (unspec_volatile [
(const_string ("<myinsn> %0,[%1] =%2"))
(const_int 0 [0x0])
(reg:SI 348)
] 21)
(const_int 0 [0x0]))
(label_ref:SI 43)
(pc)))
(clobber:SI (reg:SI 321 link))
(set:HI (reg/v:HI 346)
(unspec:HI [
(const_int 0 [0x0])
] 0))
]) -1 (nil)
(nil))
(insn 27 26 28 (nil) (set (reg/v:HI 345)
(asm_operands/v:HI ("<myinsn> %0,%0,%1") ("=r") 0 [
(reg/v:HI 346)
(reg/v:HI 345)
]
[
(asm_input:HI ("r"))
(asm_input:HI ("0"))
] -1 (nil)
(nil))
gets changed by CSE into
same as above +
(insn 27 61 28 2 0x2aaaacbab200 (set (reg/v:HI 345)
(asm_operands/v:HI ("<myinsn> %0,%0,%1") ("=r") 0 [
(reg/v:HI 345)
(reg/v:HI 345)
]
[
(asm_input:HI ("r"))
(asm_input:HI ("0"))
] -1 (nil)
(nil))
Please note one input of the asm volatile got modified.
Thanks for any help
On Fri, Sep 13, 2013 at 4:00 PM, Hendrik Greving
<hendrik.greving.intel@xxxxxxxxx> wrote:
> Hi,
>
> Can I - for a special mechanism that is defined by some special
> semantics - add a parallel side effect setting a register (e.g. from
> unspec) to a >>jump_insn?
>
> When doing that, it looks like CSE doesn't understand this.
>
> Is there a way (during expand by generating proper RTL) to tell each
> optimization phase that a side effect of a certain jump_insn is
> writing to a certain register?
>
> Thanks,
> Regards,
> Hendrik Greving
