For the records/archive: I have investigated this a little bit and ended up doing it the same way as TARGET_64BIT x86 does it: define_peephole2 and this works. Thanks, Hendrik Greving On Thu, Sep 12, 2013 at 12:02 PM, Hendrik Greving <hendrik.greving.intel@xxxxxxxxx> wrote: > Hi, this might have been asked a bizillion times, I am surprised I > couldn't easily find an answer however. If our machine supports > automatic zero extension for regular addsi3 to the full length of the > register (DI size). > > In order to avoid extra redundant zero extensions, do I > > a) add zero_extensions to addsi (I think this is not possible because > all modes have to be SI, including the set mode) > b) add a peephole to peephole optimize any redundant zero extensions > c) do something else? > > Thanks, > Regards, > Hendrik Greving
