On Tue, Jun 4, 2013 at 7:45 PM, dw <limegreensocks@xxxxxxxxx> wrote:
> And while I get an mfence instruction with this:
>
> __atomic_thread_fence(__ATOMIC_SEQ_CST);
>
> It doesn't produce quite the same instruction ordering as:
>
> asm volatile ("mfence" ::: "memory");
>
> Which makes me think that whatever __ATOMIC_SEQ_CST means, it's not the same
> as the "memory" clobber.
It's not the same as the "memory" clobber, but it should have the
effect of providing both an mfence instruction and a compiler memory
barrier.
> Also, I'm looking to support SFENCE and LFENCE,
> which these don't appear to support at all.
That is true. I think the only supported way to get those is the
Intel intrinsics _mm_sfence and _mm_lfence.
Ian
