On Thu, Apr 11, 2013 at 12:22 PM, Chung-Ju Wu <jasonwucj@xxxxxxxxx> wrote:
> 2013/4/10 Terry Guo <flameroc@xxxxxxxxx>:
>> Hi there,
>>
>> For define_peephole2, one can use (match_scratch:SI 2 "r") to require an
>> extra scratch register. I am wondering whether it is possible to require an
>> extra register for define_split?
>>
>> I am trying to split following RTL into more than one RTLs and thus need an
>> extra register.
>>
>> (define_split
>> [(set (match_operand:SF 0 "register_operand")
>> (match_operand:SF 1 "const_double_operand"))]
>> .................
>> )
>>
>> The above define_split can match its targets, but following will fail to
>> match:
>>
>> (define_split
>> [(set (match_operand:SF 0 "register_operand")
>> (match_operand:SF 1 "const_double_operand"))
>> (clobber (match_scratch:SI 2 "register_operand"))]
>> ............
>> )
>>
>> Could some one please help? Thanks in advance.
>>
>> BR,
>> Terry
>
> Hi, Terry,
>
> The split may happen before/after reload phase.
> You can use reload_completed or can_create_pseudo_p()
> to check whether you can create a new register.
>
> A sample can be refered in arm.md:
>
> (define_split
> [(set (match_operand:SI 0 "register_operand" "")
> (match_operand:SI 1 "const_int_operand" ""))]
> "TARGET_THUMB1 && satisfies_constraint_J (operands[1])"
> [(set (match_dup 2) (match_dup 1))
> (set (match_dup 0) (neg:SI (match_dup 2)))]
> "
> {
> operands[1] = GEN_INT (- INTVAL (operands[1]));
> operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
> }"
> )
>
> Also I think you can add more statement in your
> (define_expand "movsf"
> ...
> ...)
> to process const_double earlier.
>
>
> Best regards,
> jasonwucj
Thank you Jason. I will check them.
BR,
Terry
