Hi list, I'm curious about the assembly that gcc generates for the ARM target, in particular the Cortex M4, which uses the Thumb instruction set. It's not that anything is wrong, but I find it peculiar and would like to know the reason (because in my case this might be significant). Picking an arbitrary example: 80002f2: movw r2, #21512 80002f6: ands r1, r0 80002f8: movt r2, #1856 The order of instructions seems peculiar to me. What I would have expected would be: 80002f6: ands r1, r0 80002f2: movw r2, #21512 80002f8: movt r2, #1856 In particular, I often see the movw/movt pair split up, sometimes with lsls, sometimes with ldr instructions (seems arbitrary). Is this done deliberately (because for example some pipeline speedup or similar) or is this just some artifact? If if is done deliberately, can somebody maybe point me to a reference as to why this is done? Best regards, Johannes
