-------- Original-Nachricht --------
> Datum: Fri, 01 Jun 2012 14:38:02 +0200
> Von: Georg-Johann Lay <avr@xxxxxxxx>
> An: Setjem Setjem <Setjem@xxxxxx>
> CC: gcc-help@xxxxxxxxxxx
> Betreff: Re: Does a target system must support indexing?
> Setjem Setjem wrote:
> > Does a target system must support indexing? I have tried to disable
> > indexing by setting the following macros:
> >
> > #define INDEX_REG_CLASS NO_REGS
> > #define REGNO_OK_FOR_INDEX_P(num) 0
> >
> > and rejecting all addresses with side effects in the target
> > hook TARGET_LEGITIMATE_ADDRESS_P.
> >
> > But it seems that the compiler still trying to use indexes.
> > For example the compiler fails at:
> >
> > C-code:
> >
> > void fail(long long *v)
> > {
> > *v += 1;
> > }
> >
> > Failure:
> >
> > fail.c: In function 'fail':
> > fail.c:4:1: internal compiler error: in change_address_1, at
> emit-rtl.c:1933
> > Please submit a full bug report,
> > with preprocessed source if appropriate.
> > See <http://gcc.gnu.org/bugs.html> for instructions.
> >
> > Last debug info from TARGET_LEGITIMATE_ADDRESS_P:
> >
> > legitimate_address_p:
> > mode: (SI) (reload_completed) (reg_renumber):
> > (r18 ---> r18)
> > address: (plus:SI (reg/f:SI 18 r18)
> > (const_int 4 [0x4]))
> > return false
>
> This is not indexed addressing. Indexed addressing would be
> [reg+reg] or [reg + const*reg]
Does that mean in general it is possible to describe a backend without indexed addressing?
>
> > I am not sure if it fails because of the index or i made
> > some mistakes in describing the handling of long long values.
> > But still. Why the compiler tried to use indexing?
>
> Look at TARGET_LEGITIMIZE_ADDRESS and at expand time you can
> force the [reg+const] addresses into a register.
Thank you very much,
Let me get this right that expand time is the time before reload is in progress?
Now i have implemeted TARGET_LEGITIMIZE_ADDRESS:
rtx menmic_legitimize_address(rtx x, rtx oldx, enum machine_mode mode)
{
x = oldx;
#ifdef TARGET_ALL_DEBUG
fprintf( stderr, "legitimize_address:\nold\tmode: %s\n",
GET_MODE_NAME(mode));
debug_rtx(oldx);
#endif
if (GET_CODE (oldx) == PLUS && REG_P (XEXP (oldx,0)))
{
if (REG_P (XEXP (oldx,1)))
x = force_reg(GET_MODE (oldx), oldx);
else if (GET_CODE (XEXP (oldx, 1)) == CONST_INT)
{
x = force_reg(GET_MODE (oldx), oldx);
}
}
#ifdef TARGET_ALL_DEBUG
fprintf(stderr, "\nnew\tmode: %s\n", GET_MODE_NAME(mode));
debug_rtx(x);
#endif
return x;
}
Unfortunately, the problem still appears and the failure is the same.
It seems that TARGET_LEGITIMIZE_ADDRESS is only used before reload phase and the problem appears while reload is in progress.
I have attached a file with all debug information, maybe it helps to find the problem.
Best regards,
Andreas
PS:
I thought that the compiler could handle this without TARGET_LEGITIMIZE_ADDRESS, because the gcc internal manual says:
"It is not necessary for this hook to come up with a legitimate address.
The compiler has standard ways of doing so in all cases."
--
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menmic_option_override
menmic_asm_init_sections
menmic_legitimate_address_p
mode: (QI) :
address:
(mem:SI (plus:SI (reg:SI 38)
(const_int 4 [0x4])) [0 S4 A32])
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(mem:SI (symbol_ref:SI ("foo")) [0 S4 A32])
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 0 r0))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 1 r1))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 2 r2))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 3 r3))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 4 r4))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 5 r5))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 6 r6))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 7 r7))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 8 r8))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 9 r9))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 10 r10))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 11 r11))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 12 r12))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 13 r13))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 14 r14))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 15 r15))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 16 r16))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 17 r17))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 18 r18))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 19 r19))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 20 r20))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 21 r21))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 22 r22))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 23 r23))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 24 r24))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 25 r25))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 26 r26))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 27 r27))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 28 r28))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 29 r29))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 30 r30))
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (QI) :
address:
(plus:SI (plus:SI (reg:SI 18 r18)
(reg:SI 31 r31))
(const_int 4 [0x4]))
ret_val false
menmic_init_machine_status
menmic_init_machine_status
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 29 r29)
menmic_regno_ok_for_base_p: return: 29
ret_val false
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 29 r29)
menmic_regno_ok_for_base_p: return: 29
ret_val false
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg:SI 34 virtual-stack-dynamic)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg:SI 34 virtual-stack-dynamic)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg:SI 34 virtual-stack-dynamic)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg:SI 34 virtual-stack-dynamic)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg:SI 34 virtual-stack-dynamic)
ret_val true
failmenmic_init_machine_status
Analyzing compilation unit
menmic_init_cumulative_args
menmic_num_arg_regs regnums: 1
menmic_function_arg_advance:
nregs: 3
regno: 21
Performing interprocedural optimizations
<*free_lang_data> <visibility> <early_local_cleanups> <emutls> <whole-program> <inline>Assembling functions:
failmenmic_init_cumulative_args
menmic_num_arg_regs regnums: 1
menmic_function_arg
menmic_num_arg_regs regnums: 1
menmic_function_arg_advance:
nregs: 3
regno: 21
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
ret_val false
menmic_legitimate_address_p
mode: (SI) :
address:
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
ret_val false
legitimize_address:
old: mode: SI
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
new: mode: SI
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 41)
ret_val true
menmic_legitimate_address_p
mode: (DI) :
address:
(reg/f:SI 41)
ret_val true
menmic_legitimate_address_p
mode: (DI) :
address:
(reg/f:SI 41)
ret_val true
menmic_legitimate_address_p
mode: (DI) :
address:
(reg/f:SI 41)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 41)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 41)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(plus:SI (reg/f:SI 41)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (SI) :
address:
(plus:SI (reg/f:SI 41)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (SI) :
address:
(plus:SI (reg/f:SI 41)
(const_int 4 [0x4]))
ret_val false
legitimize_address:
old: mode: SI
(plus:SI (reg/f:SI 41)
(const_int 4 [0x4]))
new: mode: SI
(reg:SI 42)
menmic_legitimate_address_p
mode: (SI) :
address:
(reg:SI 42)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg:SI 42)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 42)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
ret_val false
menmic_legitimate_address_p
mode: (SI) :
address:
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
ret_val false
legitimize_address:
old: mode: SI
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
new: mode: SI
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 47)
ret_val true
menmic_legitimate_address_p
mode: (DI) :
address:
(reg/f:SI 47)
ret_val true
menmic_legitimate_address_p
mode: (DI) :
address:
(reg/f:SI 47)
ret_val true
menmic_legitimate_address_p
mode: (DI) :
address:
(reg/f:SI 47)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 47)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 47)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(plus:SI (reg/f:SI 47)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (SI) :
address:
(plus:SI (reg/f:SI 47)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (SI) :
address:
(plus:SI (reg/f:SI 47)
(const_int 4 [0x4]))
ret_val false
legitimize_address:
old: mode: SI
(plus:SI (reg/f:SI 47)
(const_int 4 [0x4]))
new: mode: SI
(reg:SI 48)
menmic_legitimate_address_p
mode: (SI) :
address:
(reg:SI 48)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg:SI 48)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 48)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 41)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 42)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 33 virtual-stack-vars)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 47)
ret_val true
menmic_legitimate_address_p
mode: (SI) :
address:
(reg/f:SI 48)
ret_val true
menmic_incoming_return_addr_rtx
menmic_incoming_return_addr_rtx
menmic_can_eliminate
menmic_can_eliminate
menmic_can_eliminate
menmic_can_eliminate
menmic_can_eliminate
menmic_can_eliminate
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 16
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 16
menmic_initial_elimination_offset
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 41)
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 41)
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 42)
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 42)
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 47)
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 47)
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 48)
ret_val true
menmic_legitimate_address_p
mode: (SI) (reg_renumber):
address:
(reg/f:SI 48)
ret_val true
menmic_can_eliminate
menmic_can_eliminate
menmic_can_eliminate
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 52
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 52
menmic_initial_elimination_offset
menmic_legitimate_address_p
mode: (DI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (DI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 12 [0xc]))
ret_val false
menmic_legitimate_address_p
mode: (DI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 20 [0x14]))
ret_val false
menmic_legitimate_address_p
mode: (DI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 28 [0x1c]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 28 [0x1c]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 28 [0x1c]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 4 [0x4]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 20 [0x14]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 20 [0x14]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 28 [0x1c]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 28 [0x1c]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 4 [0x4]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 32 [0x20]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 32 [0x20]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 8 [0x8]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 8 [0x8]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 24 [0x18]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 24 [0x18]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 32 [0x20]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 32 [0x20]))
ret_val false
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 52
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 52
menmic_initial_elimination_offset
menmic_can_eliminate
menmic_can_eliminate
menmic_frame_pointer_required_p
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60
menmic_initial_elimination_offset
menmic_legitimate_address_p
mode: (DI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (DI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 12 [0xc]))
ret_val false
menmic_legitimate_address_p
mode: (DI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 20 [0x14]))
ret_val false
menmic_legitimate_address_p
mode: (DI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 28 [0x1c]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 28 [0x1c]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 28 [0x1c]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 4 [0x4]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 20 [0x14]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 20 [0x14]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 28 [0x1c]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 28 [0x1c]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 4 [0x4]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 32 [0x20]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 32 [0x20]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 8 [0x8]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 8 [0x8]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 24 [0x18]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 24 [0x18]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 32 [0x20]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 32 [0x20]))
ret_val false
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60
menmic_initial_elimination_offset
menmic_can_eliminate
menmic_can_eliminate
menmic_frame_pointer_required_p
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60
menmic_initial_elimination_offset
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 28 [0x1c]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 28 [0x1c]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 4 [0x4]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 20 [0x14]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 20 [0x14]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 28 [0x1c]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 28 [0x1c]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 4 [0x4]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 4 [0x4]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 32 [0x20]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 32 [0x20]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 8 [0x8]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 8 [0x8]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 24 [0x18]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 24 [0x18]))
ret_val false
menmic_legitimate_address_p
mode: (SI) (strict) (reload_in_progress) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 32 [0x20]))
ret_val false
menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI) (reload_in_progress) (reg_renumber): (r49 ---> r0)
address:
(plus:SI (reg:SI 49)
(const_int 32 [0x20]))
ret_val false
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60
menmic_initial_elimination_offset
menmic_legitimate_address_p
mode: (SI) (reload_completed) (reg_renumber): (r18 ---> r18)
address:
(plus:SI (reg/f:SI 18 r18)
(const_int 4 [0x4]))
ret_val false
fail.c: In function 'fail':
fail.c:4:1: internal compiler error: in change_address_1, at emit-rtl.c:1933
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://gcc.gnu.org/bugs.html> for instructions.
