Hi Makarov, I posted a mail couple of days back. Could you throw some light on this? Thanks Ganesh ---------- Forwarded message ---------- From: ganesh gopalasubramanian <gganeshgcc@xxxxxxxxx> Date: Mon, Jan 2, 2012 at 12:22 PM Subject: Information regarding scheduler description To: gcc-help@xxxxxxxxxxx Hi, I am trying to describe my processor pipeline. Consider that I am having 5 instructions (instruction1, instruction2... instruction5). For four of those instructions, I have described the instruction reservations along with the functional units and their alternatives available for each cycle. For the fifth instruction, I haven't described the instruction reservation. What will happen now? Will the instruction be stalling my pipeline. Consider that five instruction instruction are generated as below. instruction1, instruction2, instruction3, instruction4, instruction5 My scheduler description supports the following 1. instruction1 & instruction2 can be issued as a single bundle. 2. instruction3 & instruction4 can be issued as a single bundle. Now, I don't have description about instruction5, will it stall my pipeline and get issued as a separation instruction bundle (assuming issue rate as 1)? Or should I describe the instruction reservation (for instruction5) separately along with stall information? Regards Ganesh
