My architecture doesn't have native support for half-word
loads/stores. We need to do a full word load and then use some
scratch registers to pick the relevant half word using several
operations by using a bunch of scratch registers. These operations
are done via a bunch of define_splits that use these scratches. I
have defined the define_expand and define_insn as below:
(define_expand "movhi"
[(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
(match_operand:HI 1 "general_operand" ""))
(set (match_scratch:SI 2 "") (const_int 0))
(set (match_scratch:SI 3 "") (const_int 0))
(set (match_scratch:HI 4 "") (const_int 0))
(set (match_scratch:BI 5 "") (const_int 0))])]
""
{
...
})
(define_insn "*movhi"
[(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,m")
(match_operand:HI 1 "general_operand" "r,J,I,m,r"))
(set (match_scratch:SI 2 "=r,X,X,r,r") (const_int 0))
(set (match_scratch:SI 3 "=r,X,X,r,r") (const_int 0))
(set (match_scratch:HI 4 "=r,X,X,r,r") (const_int 0))
(set (match_scratch:BI 5 "=ceq,X,X,ceq,ceq") (const_int 0))])]
""
"@
...
)
The problem that I face with this is that post reload, in the CSE and
combine passes, it looks like generating this instruction but is
unable to allocate the scratch registers (as expected). Hence it
fails while trying to match the constraints in post CSE (in function
reload_cse_simplify_operands). The scratches do not match the 'r'
constraint and hence fail. How do I prevent it from generating this
instruction post-reload? Or is there some other solution to it?
The things I have already tried:
1. Placing a " ! reload_completed " condition in the define_expand
and define_insn - it shows the same RTL INSN and says unrecognizable
instruction.
2. Changing the "set" of the scratch registers to a "clobber" - this
has no effect on the error.
I suspect that
Thanks
Ayonam
