Hi, I have been working on port with variable register widths. We have 12 16-bit registers and 4 32-bit registers. Registers r0 - r11 are 16-b wide and can be paired to form a 32-b register. Registers r12,r13,r14 and r15 are 32-bit wide and out of which r12 - argument pointer register. r13 - frame pointer register. r14 - return address register. r15 - stack pointer register. I faced a regression in gcc-torture test case "20070905-1.c" when I compile the code with -O2 or higher the test case fails with "internal compiler error: in gen_rtx_SUBREG, at emit-rtl.c:776" After analyzing the rtl dump, I figured out that below mentioned dump is the reason for the failure. (insn 46 14 47 4 20070905-1.c:17 (set (reg:HI 3 r3) (subreg:HI (reg/f:SI 13 r13) 0)) 64 {*movhi_short} (nil)) (insn 47 46 18 4 20070905-1.c:17 (set (reg:HI 4 r4 [+2 ]) (subreg:HI (reg/f:SI 13 r13) 2)) 64 {*movhi_short} (nil)) The insn 47 with subreg byte value of 2 causes the ICE in function gen_rtx_SUBREG. " gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); " You can find the current implementation of cr16 at the following link http://gcc.gnu.org/ml/gcc-patches/2011-01/msg00803.html In addition to the patch I have made couple of changes suggested by Richard Henderson. http://gcc.gnu.org/ml/gcc-patches/2011-01/msg01008.html One among them is :: #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ ? reg_classes_intersect_p (LONG_REGS, (CLASS)) \ : 0) >> LONG_REGS are 32-bit registers Please let me know if you need further information. Your help in this regard is highly appreciated. Thanks and Regards, Sumanth G