Hi, I am working with gcc-2.95.3 ported to a RISC architecture. I did a modification in the port to insert 'nop' instruction. This is done to fix a defect. When I built the compiler (with this fix) and used it to build the glibc I got the assembler error "Relocation overflow". On analysis it is found that the RISC architecture has conditional branches that can address destinations with a depth of 4000 bytes. This limitation is not considered while doing the port. After the fix I did, some conditional branches addressed destination that were beyond the 4000 bytes breaking the limitation. Now I want to fix this case as follows: 1. Conditionally branch to the maximum depth it (a conditional branch) can address (i.e. branch to a temporary place within the allowed range) 2. Then jump from there to the actual destination. For example, fix the following case: 0000 bge r0, r1, __LABEL__ 0004 ... 0008 ... 0012 ... 0016 ... .. .. 7000 ... 7004 __LABEL__: add r3, r4, r5 7008 sub r6, r4, r2 to as shown below: 0000 bge r0, r1, __TMP_LABEL__ 0004 ... 0008 ... 0012 ... 0016 ... .. .. 4000 ... 4004 __TMP_LABEL__: jmp __LABEL__ .. .. 7000 ... 7004 __LABEL__: add r3, r4, r5 7008 sub r6, r4, r2 I checked some reference ports regarding this only to find that the short conditional branches are converted to long branches as follows: -- cut --- sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", br); -- cut -- gcc-2.95.3/gcc/config/m32r/m32r.md Could someone help me to find out a reference/reference-port that I can refer to provide the fix as I have shown above. Thank you, Chandra Kumar R.
