Hi,
I am trying to port gcc-4.3.0 to a custom architecture. The high level
language selected is C.
The processor is a RISC processor and all the registers are of 32-bits wide.
The integer data type (SImode) is set as 32-bits.
I have already completed implementation to support integer data type and it
works fine. Now I am trying to support other data types such as char
(8-bits), short int (16-bits).
I have defined the following things:
1. macros in the .h file:
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < 4) \
{ \
(MODE) = SImode; \
}
#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
if ((GET_MODE_CLASS (MODE) == MODE_INT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
&& GET_MODE_SIZE (MODE) < 4) \
(MODE) = SImode;
2. md patterns for zero_extend and extend patterns, movqi and movhi.
The gcc builds successfully and also cc1 compiles the following C code. But
you can see that the generated assembly has bugs.
C code:
void main()
{
short int c;
int b;
b = c;
}
generated .s looks something like :
...function prologue..
loadHI Reg1, (frame_pointer, #-18)
storeHI Reg1,[frame_pointer, #-28]
loadSI Reg2, [frame_pointer, #-28]
ashiftleft Reg1,Reg2,#16
ashiftright Reg1,Reg1,#16
storeSI Reg1,[frame_pointer, #-16]
...function epilogue
expected .s is:
...function prologue..
loadHI Reg1, (frame_pointer, #-18)
storeSI Reg1,[frame_pointer, #-16]
...function epilogue
I am not able to find out why extra load, store and shift instructions are
generated.
-Rajeshwari
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