Andrew Haley wrote:
> Leonitis wrote:
>> Andrew Haley wrote:
>>> Please send a test case that displays the problem.
>>> The test you just sent doesn't even compile for me.
>>>
>> Sorry about that. While typing the post, I was changing some variable names
>> to avoid confusion and the edit to the mistake was not submitted to the
>> mailing list.
>>
>> I ran the test that you wrote up and here's what happens:
>>
>> For no optimization, -O2, and -O3:
>> 3fffffff
>> 3fffffff00000001
>>
>> For -O:
>> 3fffffff00000001
>> 3fffffff00000001
>>
>> With the test I was running before, -O2 was the only one that didn't work.
>>
>> I'm beginning to suspect an alignment issue. Again, STRD requires the target
>> address to be 8-byte aligned.
>
> Could be. Was this with exactly the test code I posted, no changes?
I can't find any asm better than this:
inline long long MULT32_32_64_3(int a, int b)
{
long long res;
asm volatile("SMULL %Q0, %R0, %[a], %[b]\n\t"
: "=&r" (res)
: [a] "r" (a), [b] "r" (b));
return res;
}
/* An explanation of the 'Q', 'R' and 'H' register operands:
In a pair of registers containing a DI or DF value the 'Q'
operand returns the register number of the register containing
the least significant part of the value. The 'R' operand returns
the register number of the register containing the most
significant part of the value.
Ian is right, though:
long long test3 (int a, int b)
{
return (long long)a * b;
}
generates
50 test3:
51 @ args = 0, pretend = 0, frame = 0
52 @ frame_needed = 0, uses_anonymous_args = 0
53 @ link register save eliminated.
54 0028 9120C3E0 smull r2, r3, r1, r0
55 002c 0310A0E1 mov r1, r3
56 0030 0200A0E1 mov r0, r2
57 0034 1EFF2FE1 bx lr
Andrew.
