He Xiao wrote:
When I finished the scheduler, I got a strange phenomenon:
The CPI is reduced, but the total execution cycles are dramatically increased.
I read THE GNU INSTRUCTION SCHEDULER written by Michael D. Tiemann,
which mentioned a similar situation in sparc arch( chapter 7 extension
and future work), This article infromed me that register pressure is a
really big problem during instruction scheduling. I know I must ignore
something critical, but I don't know what it is. Is anyone there
helping me? Thank in advance.
You should use gcc-help mailing list for such questions.
Michael Tiemann's scheduler was removed long ago (I don't remember
exactly but about 10 years ago). That was a list BB block scheduler
processing dependencies backward.
The current scheduler (except schedulers used for Itanium) is based on
IBM Haifa Lab interblock scheduler.
But the problem is still the same: usage of Haifa scheduler before RA
may result in worse code in average for architectures with small or
moderate size register file. That is because the scheduler is not
register pressure aware. And that is one reason why insn scheduler
before RA are switched off for x86/x86_64.
Some work on register pressure sensitive insn scheduling is being done.
I hope this work will be available for GCC4.5.
