Matthew Woehlke wrote:
Eljay Love-Jensen wrote:
Hi Matthew,
Huh? I thought SMP hardware is required to be responsible for cache
syncing in such an instance...
No. Alas. Perhaps on some SMP hardware, but not all.
Huh. I'm pretty sure I read about Intel chips doing exactly this.
They do, but you'd be unwise to depend on it.
A list
of what architectures do or do not provide cache synchronization would
be interesting.
Yes, but again, it's not a good idea to use it. gcc has all the atomic
primitives you need -- see "Built-in functions for atomic memory access".
Unfortunately not all hardware supports these, so people oten use
mutexes anyway.
For the hardware I used, which definitely did not have that feature,
that's
why the pthread library emitted a memory barrier around the mutex: to
ensure the caches are synchronized.
Bleh. I wonder what percentage of (multithreaded, at least) software has
subtle bugs from exactly this, because I'm sure it's very large.
I don't agree. I think most authors of multi-threaded programs are
aware of the problem and use the correct primitives.
Andrew.
