Hello, >VVc_demo$(OBJ_EXT) : a.cpp b.cpp c.cpp > g++ -o $@ -c VVc_demo.cpp >(Usually you'd add VVc_demo.cpp itself to the dependency list as well.) Thanks but I forgot to say that there are some .h files too (it was my fault). I add some thing like this: VVc_demo.moc: VVc_demo.cpp $(QT_MOC) -o VVc_demo.moc VVc_demo.cpp VVc_demo$(OBJ_EXT): VVc_demo.moc VVc_diagram_2.h Polygon_Voronoi_diagram_2.h g++ -o $@ -c VVc_demo.cpp VVc_demo$(EXE_EXT): VVc_demo$(OBJ_EXT) $(CGAL_CXX) $(LIBPATH) $(EXE_OPT)VVc_demo VVc_demo$(OBJ_EXT) $(LDFLAGS) but it says: [mahmood@Milky-way VVc_diagram_2]$ make make: *** No rule to make target `VVc_diagram_2.h', needed by `VVc_demo.o'. Stop. What should I do now? John (Eljay) Love-Jensen wrote: > > Hi Mahmoodn, > >> I want to tell make that compile VVc_demo.cpp whenever "a.cpp" or "b.cpp" >> or >> "c.cpp" or ... changed. >> How can I do that? > > VVc_demo$(OBJ_EXT) : a.cpp b.cpp c.cpp > g++ -o $@ -c VVc_demo.cpp > > (Usually you'd add VVc_demo.cpp itself to the dependency list as well.) > > HTH, > --Eljay > > > > -- View this message in context: http://www.nabble.com/need-help-for-editing-a-makefile-tp14269485p14290372.html Sent from the gcc - Help mailing list archive at Nabble.com.
