"Sync ma" <sync.jma@xxxxxxxxx> writes: > I'm confused about asm codes generator by mipsel-linux-gcc, > .text_rom:9000F788 lw $v1, 0x148+arg_4($fp) > .text_rom:9000F78C lw $v0, 0($v1) > as I know, mips has a load delay slot, and there should not be any > instruction use reg '$v1' before the slot on this situation. Only MIPS ISA I has a load delay slot. Processors which implement later ISAs do not require it. > Compile options: > -march=mips32 -mtune=r4600 -mabi=32 -G 0 -ansi -fno-builtin > -fdelayed-branch -fthread-jumps -fno-pic -mno-abicalls -O0 -g > -fschedule-insns2 -msoft-float You are compiling for the MIPS32 ISA, not the MIPS I ISA. MIPS32 does not have a load delay slot. (Yes, changing from ISA names like I to ISA names like 32 is an incredibly bad idea, but it's not our fault.) Ian
