Rask Ingemann Lambertsen <rask@xxxxxxxxxx> writes: > When it comes to a back end solution, one existing target (MT) has an > option to not generate byte loads and stores, and there was a long thread > about modifying the ARM back end to generate byte writes such that, at the > hardware level, they would become a cache line wide read-modify-write > access. Search the GCC mailing list for this: > > Modifying ARM code generator for elimination of 8bit writes - need help > > The ARM solution relies on assistance form the hardware, so I suggest you > look at the MT back end first to see if it does something clever. There is no doubt that gcc can do this on a per-compilation basis. It's not particularly difficult if you're familiar with the gcc backend. I think it would take quite a bit more work to do it on per-pointer basis. Ian
